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A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays
Abstract
This paper presents an ADC-free compute-in-memory (CIM) RRAM-based macro, exploiting the fully analog intra-/inter-array computation. The main contributions include: 1) a lightweight input-encoding scheme based on pulse-width modulation (PWM), which improves the compute throughput by ~7 times; 2) a fully analog data processing manner between sub-arrays without explicit ADCs, which does not introduce quantization loss and saves the power by a factor of 11.6. The 40nm prototype chip with TSMC RRAM achieves energy efficiency of 421.53 TOPS/W and compute efficiency of 360 GOPS/mm2(normalized to binary operation) at 100MHz.
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“Although several compute-in-memory or near-memory approaches based on SRAMs and digital compute35–38 have been presented in the literature, most of these do not address the energy and time costs of reloading weights, thus making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult.”
From An analog-AI chip for energy-efficient speech recognition and transcription (2023) · cites this paper as [34]
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Research works printed but not linked: 7
- yang, 2019, ISSCC
- chen, 2018, ISSCC
- yang, 2019, ISSCC
- xue, 2021, ISSCC
- li, 2021, CICC
- yu, 2020, CICC
- yu, 2021, IEEE Circuits Syst Mag
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An analog-AI chip for energy-efficient speech recognition and transcription
Ambrogio, S., Narayanan, P., Okazaki, A., Fasoli, A., Mackin, C., Hosokawa, K., Nomura, A., Yasuda, T., Chen, A., Friz, A., et al. (2023) · Nature · doi:10.1038/s41586-023-06337-5 · Cited by 269
“However, several NVM compute-in-memory studies have focused on the macro-level 32,34,39,40,41 , without accounting for data transport, control or chip infrastructure (such as clocking) costs.”
BackgroundProgramming memristor arrays with arbitrarily high precision for analog computing
Song, W., Rao, M., Li, Y., Li, C., Zhuo, Y., Cai, F., Wu, M.-C., Yin, W., Zongze, L., Wei, Q., et al. (2024) · Science · doi:10.1126/science.adi9405 · Cited by 217
Ye, W., Wang, L., Zhou, Z., An, J., Li, W., Gao, H., Li, Z., Yue, J., Hu, H., Xu, X., et al. (2023) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2023.3280357 · Cited by 66
Self-citationWang, Z., Song, Y., Zhang, G., Luo, Q., Xu, K., Gao, D., Yu, B., Loke, D. K., Zhong, S., & Zhang, Y. (2024) · International Journal of Extreme Manufacturing · doi:10.1088/2631-7990/ad2fea · Cited by 49
In-Memory Computing for Machine Learning and Deep Learning
Lepri, N., Glukhov, A., Cattaneo, L., Farronato, M., Mannocci, P., & Ielmini, D. (2023) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2023.3265875 · Cited by 52
Metadata
- Authors
- Jiang, H., Li, W., Huang, S., & Yu, S.
- Affiliations
- Georgia Institute of Technology (US)
- Venue
- 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
- Publisher
- IEEE
- Published
- 2022-06-12
- Pages
- 266-267
- OpenAlex
- W4286571956
- Cited by
- 58
- References
- 0
- Citations by year
- 2026: 12 · 2025: 10 · 2024: 17 · 2023: 15 · 2022: 4
- FWCI
- 18.60
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Analog and Mixed-Signal Circuit Design
- Keywords
- in-memory computing, resistive random access memory, pulse width modulation, energy-efficient computing, 40-nm CMOS
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