Cited by 38Advancements in Photolithography TechniquesVLSI and FPGA Design TechniquesLow-power high-performance VLSI design

The DOI matches its Crossref record; 58 of the 58 references it cites were found in a registry or an index.

Pushing multiple patterning in sub-10nm: are we ready?

Pan, David Z., Liebmann, Lars, Yu, Bei, Xu, Xiaoqing, Lin, Yibo·2015·Proceedings of the 52nd Annual Design Automation Conference

Abstract

Due to elongated delay of extreme ultraviolet lithography (EUVL), the semiconductor industry has been pushing the 193nm immersion lithopgrahy using multiple patterning to print critical features in 22nm/14nm technology nodes and beyond. Multiple patterning lithography (MPL) poses many new challenges to both mask design and IC physical design. The mask layout decomposition problem has been extensively studied, first on double patterning, then on triple or even quadruple patterning. Meanwhile, many studies have shown that it is very important to consider MPL implications at early physical design stages so that the overall design and manufacturing closure can be reached. In this paper, we provide a comprehensive overview on the state-of-the-art research results for MPL, from synergistic mask synthesis to physical design. We will also discuss the open problems as to pushing multiple patterning in sub-10nm.

Overview

Integrity signals

Registry

Crossref · 10.1145/2744769.2747940

Cites

58 of 58 references verified0 citation errors · 0 not checkable

Statistics

Recomputing p-values needs the paper’s full text.

Verification

Claims the paper makes

This paper’s full text isn’t openly available, so its claims and self-check weren’t run. The registry and citation checks still apply.

Citations

Cites

Flagged first, then by citations

Research works printed but not linked: 3

  1. V. Wiaux , S. Verhaegen , S. Cheng , F. Iwamoto , P. Jaenen , M. Maenhoudt , T. Matsuda , S. Postnikov et al., "Split and design guidelines for double patterning," in Proceedings of SPIE , vol. 6924 , 2008 . V. Wiaux, S. Verhaegen, S. Cheng, F. Iwamoto, P. Jaenen, M. Maenhoudt, T. Matsuda, S. Postnikov et al., "Split and design guidelines for double patterning," in Proceedings of SPIE, vol. 6924, 2008.
  2. Y. Borodovsky , "MPProcessing for MPProcessors," in Maskless Lithography and Multibeam Mask Writer Workshop , 2010 . Y. Borodovsky, "MPProcessing for MPProcessors," in Maskless Lithography and Multibeam Mask Writer Workshop, 2010.
  3. K. B. Agarwal , C. J. Alpert , Z. Li , G.-J. Nam , and N. Viswanathan , " Multi-patterning lithography aware cell placement in integrated circuit design ," Jul. 23 2013 , US Patent 8,495,548. K. B. Agarwal, C. J. Alpert, Z. Li, G.-J. Nam, and N. Viswanathan, "Multi-patterning lithography aware cell placement in integrated circuit design," Jul. 23 2013, US Patent 8,495,548.

Cited by

Sorted by citations

Metadata

Authors
Pan, D. Z., Liebmann, L., Yu, B., Xu, X., & Lin, Y.
Affiliations
  • The University of Texas at Austin (US)
  • IBM (United States) (US)
Venue
Proceedings of the 52nd Annual Design Automation Conference
Publisher
ACM
Published
2015-06-07
Pages
1-6
ISSN
0738-100X (ISSN-L)
OpenAlex
W1996055445
Cited by
38
References
58
Citations by year
2026: 4 · 2025: 3 · 2024: 4 · 2023: 2 · 2022: 1 · 2021: 1 · 2020: 4 · 2019: 1 · 2018: 4 · 2017: 11 · 2016: 3
FWCI
7.43
Type
conference paper
Language
en
Open access
closed
Locations
ACM/IEEE Design Automation Conference (DAC) (publishedVersion)
Funders
National Science Foundation
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Photolithography Techniques
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
Keywords
193 nm immersion lithography, mask synthesis, physical design, double patterning, design for manufacturing, design closure

About these checks

Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.

Statistics and arithmetic are recomputed, not judged.

Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.

What counts as a claim ›How we measure confidence ›How we check this ›

Are you an author, or do you see a problem with this page? Request a review