The DOI matches its Crossref record; 33 of the 33 references it cites were found in a registry or an index.
Maximizing CNN Accelerator Efficiency Through Resource Partitioning
Abstract
Convolutional neural networks (CNNs) are revolutionizing machine learning, but they present significant computational challenges. Recently, many FPGA-based accelerators have been proposed to improve the performance and efficiency of CNNs. Current approaches construct a single processor that computes the CNN layers one at a time; the processor is optimized to maximize the throughput at which the collection of layers is computed. However, this approach leads to inefficient designs because the same processor structure is used to compute CNN layers of radically varying dimensions.
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Cites
ImageNet classification with deep convolutional neural networks
Krizhevsky, A., Sutskever, I., & Hinton, G. E. (2017) · Communications of the ACM · doi:10.1145/3065386 · Cited by 112,155
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SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <0.5MB model size
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Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
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ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars
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Cited by
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
Nguyen, D. T., Nguyen, T. N., Kim, H., & Lee, H.-J. (2019) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2019.2905242 · Cited by 435
A survey of FPGA-based accelerators for convolutional neural networks
Mittal, S. (2020) · Neural Computing and Applications · doi:10.1007/s00521-018-3761-1 · Cited by 429
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference
Ankit, A., Hajj, I. E., Chalamalasetti, S. R., Ndu, G., Foltin, M., Williams, R. S., Faraboschi, P., Hwu, W.-M. W., Strachan, J. P., Roy, K., et al. (2019) · Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems · doi:10.1145/3297858.3304049 · Cited by 424
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture
Shao, Y. S., Clemons, J., Venkatesan, R., Zimmer, B., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., et al. (2019) · Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture · doi:10.1145/3352460.3358302 · Cited by 406
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads
Kwon, H., Lai, L., Pellauer, M., Krishna, T., Chen, Y.-H., & Chandra, V. (2021) · 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA) · doi:10.1109/hpca51647.2021.00016 · Cited by 144
Metadata
- Authors
- Shen, Y., Ferdman, M., & Milder, P.
- Venue
- Proceedings of the 44th Annual International Symposium on Computer Architecture
- Publisher
- ACM
- Published
- 2017-06-24
- Pages
- 535-547
- ISSN
- 1063-6897 (ISSN-L)
- OpenAlex
- W2466675884
- Cited by
- 284
- References
- 33
- FWCI
- 27.33
- Type
- conference paper
- Language
- en
- Open access
- closed
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