Superneurons: dynamic GPU memory management for training deep neural networks
Open accessAbstract
Going deeper and wider in neural architectures improves their accuracy, while the limited GPU DRAM places an undesired restriction on the network design domain. Deep Learning (DL) practitioners either need to change to less desired network architectures, or nontrivially dissect a network across multiGPUs. These distract DL practitioners from concentrating on their original machine learning tasks. We present SuperNeurons: a dynamic GPU memory scheduling runtime to enable the network training far beyond the GPU DRAM capacity. SuperNeurons features 3 memory optimizations, Liveness Analysis, Unified Tensor Pool, and Cost-Aware Recomputation; together they effectively reduce the network-wide peak memory usage down to the maximal memory usage among layers. We also address the performance issues in these memory-saving techniques. Given the limited GPU DRAM, SuperNeurons not only provisions the necessary memory for the training, but also dynamically allocates the memory for convolution workspaces to achieve the high performance. Evaluations against Caffe, Torch, MXNet and TensorFlow have demonstrated that SuperNeurons trains at least 3.2432 deeper network than current ones with the leading performance. Particularly, SuperNeurons can train ResNet2500 that has 104 basic network layers on a 12GB K40c.
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On the Limits of Parallelizing Convolutional Neural Networks on GPUs
Pourghassemi, B., Zhang, C., Lee, J. H., & Chandramowlishwaran, A. M. (2020) · ACM Symposium on Parallelism in Algorithms and Architectures (SPAA) · doi:10.1145/3350755.3400266 · Cited by 13 · see citing works
STR: Hybrid Tensor Re-Generation to Break Memory Wall for DNN Training
Zong, Z., Lin, L., Lin, L., Wen, L., & Sun, Y. (2023) · IEEE Transactions on Parallel and Distributed Systems · doi:10.1109/tpds.2023.3266110 · Cited by 12 · see citing works
CoTrain: Efficient Scheduling for Large-Model Training upon GPU and CPU in Parallel
Li, Z., Cao, Q., Chen, Y., & Yan, W. (2023) · Proceedings of the International Conference on Parallel Processing · doi:10.1145/3605573.3605647 · Cited by 12 · see citing works
HOME: A Holistic GPU Memory Management Framework for Deep Learning
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Zhang, M., Hu, Z., & Li, M. (2021) · IEEE International Parallel and Distributed Processing Symposium (IPDPS) · doi:10.1109/ipdps49936.2021.00024 · Cited by 12 · see citing works
Han, M., & Baek, W. (2021) · International Conference on Parallel Architectures and Compilation Techniques (PACT) · doi:10.1109/pact52795.2021.00014 · Cited by 11 · see citing works
Only Buffer When You Need To: Reducing On-chip GPU Traffic with Reconfigurable Local Atomic Buffers
Dalmia, P., Mahapatra, R., & Sinclair, M. D. (2022) · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · doi:10.1109/hpca53966.2022.00056 · Cited by 11 · see citing works
Enabling Large Dynamic Neural Network Training with Learning-based Memory Management
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CoGNN: Efficient Scheduling for Concurrent GNN Training on GPUs
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CSWAP: A Self-Tuning Compression Framework for Accelerating Tensor Swapping in GPUs
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Angel-PTM: A Scalable and Economical Large-Scale Pre-Training System in Tencent
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Breaking the Memory Wall for Heterogeneous Federated Learning via Model Splitting
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AdaShadow: Responsive Test-time Model Adaptation in Non-stationary Mobile Environments
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Wireless Edge Computing With Latency and Reliability Guarantees
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A Scalable, Efficient, and Robust Dynamic Memory Management Library for HLS-based FPGAs
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Adaptive Sparse Deep Neural Network Inference on Resource-Constrained Cost-Efficient GPUs
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Profiling based out-of-core Hybrid method for large neural networks
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Self-citationThe Case for Storage Optimization Decoupling in Deep Learning Frameworks
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VGA: Hardware Accelerator for Scalable Long Sequence Model Inference
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Exploring Means to Enhance the Efficiency of GPU Bitmap Index Query Processing
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Zhang, X., Xia, H., Zhuang, D., Sun, H., Fu, X., Taylor, M. B., & Song, S. L. (2021) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1109/isca52012.2021.00051 · Cited by 7 · see citing works
Self-citation
- Authors
- Wang, L., Ye, J., Zhao, Y., Wu, W., Li, A., Song, S. L., Xu, Z., & Kraska, T.
- Affiliations
- Brown University (US)
- University of Electronic Science and Technology of China (CN)
- Los Alamos National Laboratory (US)
- Pacific Northwest National Laboratory (US)
- Venue
- Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
- Publisher
- ACM
- Published
- 2018-02-10
- Pages
- 41-53
- OpenAlex
- W4301361180
- Cited by
- 175
- References
- 28
- Citations by year
- 2026: 6 · 2025: 14 · 2024: 31 · 2023: 26 · 2022: 27 · 2021: 25 · 2020: 23 · 2019: 20 · 2018: 3
- FWCI
- 15.26
- Type
- conference paper
- Language
- en
- Open access
- bronze
- doi.org
- Locations
- ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (publishedVersion)
- Funders
- VMware
- Mellanox
- Oracle
- Natural Science Foundation of China (61572111)
- DARPA (16-43-D3M-FP-040)
- Central Universities of China (ZYGX2016Z003)
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Information Systems › Cloud Computing and Resource Management
- Keywords
- GPU memory management, deep neural network training, memory optimization, liveness analysis, dynamic memory allocation, multi-GPU training
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