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Wafer-scale silicon photonic switches beyond die size limit
Open accessAbstract
Fast optical switches have been proposed as a promising alternative to enable continual scaling of data centers with increasing size and data rates. Silicon photonics is a compelling platform for large-scale integrated photonic switches, leveraging advanced manufacturing foundries for electronic integrated circuits. In the past decade, the port counts of silicon photonic switches have increased steadily to 128×128. Further scaling of the switch is constrained by the maximum reticle size (2–3 cm) of lithography tools. Here, we propose to use wafer-scale integration to overcome the die size limit. As a proof of concept demonstration, we fabricated a 240×240 switch by lithographically stitching a 3×3 array of identical 80×80 switch blocks across reticle boundaries. Stitching loss is substantially reduced (0.004 dB) by tapering the waveguide width to 10 μm. The fabricated switch on a 4 cm×4 cm chip exhibits a maximum on-chip loss of 9.8 dB, an ON/OFF ratio of 70 dB, and switching times of less than 400 ns. To our knowledge, this is the largest integrated photonic switch ever reported. The loss-to-port count ratio (0.04 dB/port) is also the lowest.
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“one of the largest-scale PICs today, a 240 × 240 silicon photonic switch matrix with 57,600 individual switching elements, has been demonstrated experimentally by combining MEMS with silicon photonic waveguides40.”
From Integrated silicon photonic MEMS (2023) · cites this paper as [40]
In the citing paper
“The recently demonstrated large-scale silicon photonic MEMS switch matrix40 and large-scale silicon photonic MEMS LiDAR41 clearly show the potential of the combination of silicon photonics and MEMS.”
From Integrated silicon photonic MEMS (2023) · cites this paper as [40]
In the citing paper
“Even VLSI (>10,000 components) prototypes have now been demonstrated30,32,34.”
From Roadmapping the next generation of silicon photonics (2024) · cites this paper as [34]
In the citing paper
“but technologies such as MEMS/NOEMS look promising34.”
From Roadmapping the next generation of silicon photonics (2024) · cites this paper as [34]
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Metadata
- Authors
- Seok, T. J., Kwon, K., Henriksson, J., Luo, J., & Wu, M. C.
- Affiliations
- Gwangju Institute of Science and Technology (KR)
- University of California, Berkeley (US)
- Venue
- Optica
- Publisher
- Optica Publishing Group
- Published
- 2019-04-12
- Volume
- 6
- Issue
- 4
- Pages
- 490
- ISSN
- 2334-2536 (ISSN-L)
- OpenAlex
- W2937088522
- Cited by
- 214
- References
- 22
- Citations by year
- 2026: 19 · 2025: 38 · 2024: 31 · 2023: 25 · 2022: 33 · 2021: 32 · 2020: 22 · 2019: 12
- FWCI
- 8.90
- Type
- journal article
- Language
- en
- Open access
- gold
- doi.org
- Locations
- Optica (publishedVersion)
- OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) (submittedVersion)
- Funders
- Advanced Research Projects Agency—Energy (DE-AR0000849)
- National Science Foundation (1827633, EEC-0812072)
- UC Berkeley
- National Research Foundation of Korea (2018R1C1B6005302)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Photonic and Optical Devices
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Optical Network Technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Semiconductor Lasers and Optical Devices
- Keywords
- silicon photonic switches, wafer-scale integration, waveguide tapering, on-chip loss, switching time, data center optical interconnects
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