The DOI matches its Crossref record; 1 of the 1 references it cites were found in a registry or an index.
Mechanism and Control Strategies for Current Sharing in Multi-Chip Parallel Automotive Power Modules
Abstract
Multi-chip parallel power modules are highly favored in applications requiring high capacity and high switching frequency. However, the dynamic current imbalance between parallel chips caused by asymmetric layouts limits the available capacity. This paper presents a method to optimize dynamic current distribution by adjusting the lengths and connection points of bond wires. For the first time, a response surface model and nonlinear constraint optimization algorithm are introduced, along with parameter analysis based on finite element methods, to establish the response surface models for the parasitic inductance of bond wires and DBC (direct bonded copper). By leveraging the optimization goals for parasitic inductance and the analytical expressions of all response surfaces, the dynamic current sharing issue was transformed into a nonlinear constrained optimization problem. The solution to this optimization problem identified the optimal connection points for the bond wires, enhancing dynamic current sharing performance. Simulations and experiments were conducted, revealing that the optimized automotive-grade module exhibited a significant reduction in current differences between parallel branches, from 41.7% to 5.03% compared with the original design. This indicated that the proposed optimization scheme for adjusting bond wire connection points could significantly mitigate current disparities, thereby markedly improving current distribution uniformity.
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Citations
Cites
An Effective Current Balancing Method for Inverters With Paralleled Silicon Carbide Power Modules
Lin, N., Zhao, Y., & Mantooth, H. A. (2023) · IEEE Transactions on Industry Applications · doi:10.1109/tia.2023.3306750 · Cited by 13
Research works printed but not linked: 17
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- Wen, 2021, Active gate driver for improving current sharing performance of paralleled high-power SiC MOSFET modules, IEEE Trans. Power Electron., 36, 1491, 10.1109/TPEL.2020.3006071 · DOI · Paper page
- Zhang, 2023, Common source inductance compensation technique for dynamic current balancing in SiC MOSFETs parallel operations, IEEE Trans. Power Electron., 38, 13944, 10.1109/TPEL.2023.3302769 · DOI
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Metadata
- Authors
- Jiang, Y., Li, X., & Ma, K.
- Venue
- Electronics
- Publisher
- MDPI AG
- Published
- 2024-11-25
- Volume
- 13
- Issue
- 23
- Pages
- 4654
- ISSN
- 2079-9292
- Cited by
- 2
- References
- 1
- Language
- en
- Funders
- Wuhan Textile University (STRZ202225, STRZ202406)
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