Chang, Meng-Fan

Neuro-inspired computing chips

Zhang, W., Gao, B., Tang, J., Yao, P., Yu, S., Chang, M.-F., Yoo, H.-J., Qian, H., & Wu, H. (2020) · Nature Electronics

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 892

Hardware implementation of memristor-based artificial neural networks

Aguirre, F., Sebastian, A., Le Gallo, M., Song, W., Wang, T., Yang, J. J., Lu, W., Chang, M.-F., Ielmini, D., Yang, Y., et al. (2024) · Nature Communications

Advanced Memory and Neural ComputingNeural Networks and Applications

Cited by 564

16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

Chih, Y.-D., Lee, P.-H., Fujiwara, H., Shih, Y.-C., Lee, C.-F., Naous, R., Chen, Y.-L., Lo, C.-P., Lu, C.-H., Mori, H., et al. (2021) · 2021 IEEE International Solid- State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 384

33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing

Liu, Q., Gao, B., Yao, P., Wu, D., Chen, J., Pang, Y., Zhang, W., Liao, Y., Xue, C.-X., Chen, W.-H., et al. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC)

Advanced Memory and Neural ComputingAnalog and Mixed-Signal Circuit Design

Cited by 308

CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors

Chen, W.-H., Dou, C., Li, K.-X., Lin, W.-Y., Li, P.-Y., Huang, J.-H., Wang, J.-H., Wei, W.-C., Xue, C.-X., Chiu, Y.-C., et al. (2019) · Nature Electronics

Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices

Cited by 276

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

Khwa, W.-S., Chen, J.-J., Li, J.-F., Si, X., Yang, E.-Y., Sun, X., Liu, R., Chen, P.-Y., Li, Q., Yu, S., et al. (2018) · 2018 IEEE International Solid - State Circuits Conference - (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 260

15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices

Xue, C.-X., Huang, T.-Y., Liu, J.-S., Chang, T.-W., Kao, H.-Y., Wang, J.-H., Liu, T.-W., Wei, S.-Y., Huang, S.-P., Wei, W.-C., et al. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 230

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Su, J.-W., Chou, Y.-C., Liu, R., Liu, T.-W., Lu, P.-J., Wu, P.-C., Chung, Y.-L., Hung, L.-Y., Ren, J.-S., Pan, T., et al. (2021) · 2021 IEEE International Solid-State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 207

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

Su, J.-W., Si, X., Chou, Y.-C., Chang, T.-W., Huang, W.-H., Tu, Y.-N., Liu, R., Lu, P.-J., Liu, T.-W., Wang, J.-H., et al. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 189

16.1 A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices

Xue, C.-X., Hung, J.-M., Kao, H.-Y., Huang, Y.-H., Huang, S.-P., Chang, F.-C., Chen, P., Liu, T.-W., Jhang, C.-J., Su, C.-I., et al. (2021) · 2021 IEEE International Solid- State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 182

A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

Xue, C.-X., Chiu, Y.-C., Liu, T.-W., Huang, T.-Y., Liu, J.-S., Chang, T.-W., Kao, H.-Y., Wang, J.-H., Wei, S.-Y., Lee, C.-Y., et al. (2020) · Nature Electronics

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 181

A computing-in-memory macro based on three-dimensional resistive random-access memory

Huo, Q., Yang, Y., Wang, Y., Lei, D., Fu, X., Ren, Q., Xu, X., Luo, Q., Xing, G., Chen, C., et al. (2022) · Nature Electronics

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 159

Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing

Wen, T.-H., Hung, J.-M., Huang, W.-H., Jhang, C.-J., Lo, Y.-C., Hsu, H.-H., Ke, Z.-E., Chen, Y.-C., Chin, Y.-H., Su, C.-I., et al. (2024) · Science

Advanced Memory and Neural ComputingParallel Computing and Optimization Techniques

Cited by 131

An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices

Hung, J.-M., Huang, Y.-H., Huang, S.-P., Chang, F.-C., Wen, T.-H., Su, C.-I., Khwa, W.-S., Lo, C.-C., Liu, R.-S., Hsieh, C.-C., et al. (2022) · 2022 IEEE International Solid- State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 125

A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices

Khwa, W.-S., Chiu, Y.-C., Jhang, C.-J., Huang, S.-P., Lee, C.-Y., Wen, T.-H., Chang, F.-C., Yu, S.-M., Lee, T.-Y., & Chang, M.-F. (2022) · 2022 IEEE International Solid- State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 125

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification

Yoon, J.-H., Chang, M., Khwa, W.-S., Chih, Y.-D., Chang, M.-F., & Raychowdhury, A. (2021) · 2021 IEEE International Solid- State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices

Cited by 86

A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme

Chen, W.-H., Lin, W.-J., Lai, L.-Y., Li, S., Hsu, C.-H., Lin, H.-T., Lee, H.-Y., Su, J.-W., Xie, Y., Sheu, S.-S., et al. (2017) · 2017 IEEE International Electron Devices Meeting (IEDM)

Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices

Cited by 73

A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory

Su, F., Chen, W.-H., Xia, L., Lo, C.-P., Tang, T., Wang, Z., Hsu, K.-H., Cheng, M., Li, J.-Y., Xie, Y., et al. (2017) · 2017 Symposium on VLSI Technology

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 69