The DOI matches its Crossref record; 2 of the 2 references it cites were found in a registry or an index.
DRAMSim2: A Cycle Accurate Memory System Simulator
Abstract
In this paper we present DRAMSim2, a cycle accurate memory system simulator. The goal of DRAMSim2 is to be an accurate and publicly available DDR2/3 memory system model which can be used in both full system and trace-based simulations. We describe the process of validating DRAMSim2 timing against manufacturer Verilog models in an effort to prove the accuracy of simulation results. We outline the combination of DRAMSim2 with a cycle-accurate x86 simulator that can be used to perform full system simulations. Finally, we discuss DRAMVis, a visualization tool that can be used to graph and compare the results of DRAMSim2 simulations.
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Citations
Cites
The PARSEC benchmark suite: characterization and architectural implications
Bienia, C., Kumar, S., Singh, J. P., & Li, K. (2008) · Proceedings of the 17th international conference on Parallel architectures and compilation techniques · doi:10.1145/1454115.1454128 · Cited by 3,444
Memory Systems: Cache, DRAM, Disk
Jacob, B., Ng, S. W., & Wang, D. (2007) · Cited by 608
Self-citation
Cited by
RAIDR: Retention-Aware Intelligent DRAM Refresh
Liu, J., Jaiyen, B., Veras, R., & Mutlu, O. (2012) · ACM SIGARCH Computer Architecture News · doi:10.1145/2366231.2337161 · Cited by 444
Lee, S., Kang, S.-H., Lee, J., Kim, H., Lee, E., Seo, S., Yoon, H., Lee, S., Lim, K., Shin, H., et al. (2021) · 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca52012.2021.00013 · Cited by 269
Practical Near-Data Processing for In-Memory Analytics Frameworks
Gao, M., Ayers, G., & Kozyrakis, C. (2015) · 2015 International Conference on Parallel Architecture and Compilation (PACT) · doi:10.1109/pact.2015.22 · Cited by 266
Big/little deep neural network for ultra low power inference
Park, E., Kim, D., Kim, S., Kim, Y.-D., Kim, G., Yoon, S., & Yoo, S. (2015) · 2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) · doi:10.1109/codesisss.2015.7331375 · Cited by 130
GOBO: Quantizing Attention-Based NLP Models for Low Latency and Energy Efficient Inference
Zadeh, A. H., Edo, I., Awad, O. M., & Moshovos, A. (2020) · 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1109/micro50266.2020.00071 · Cited by 10
Metadata
- Authors
- Rosenfeld, P., Cooper-Balis, E., & Jacob, B.
- Venue
- IEEE Computer Architecture Letters
- Published
- 2011-01
- Volume
- 10
- Issue
- 1
- Pages
- 16-19
- ISSN
- 1556-6056 (ISSN-L)
- OpenAlex
- W2162639668
- Cited by
- 908
- References
- 2
- FWCI
- 77.58
- Type
- journal article
- Language
- en
- Open access
- closed
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Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
