The DOI matches its Crossref record; 27 of the 27 references it cites were found in a registry or an index.
RAIDR: Retention-Aware Intelligent DRAM Refresh
Abstract
Dynamic random-access memory (DRAM) is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh operations waste energy and degrade system performance by interfering with memory accesses. The negative effects of DRAM refresh increase as DRAM device capacity increases. Existing DRAM devices refresh all cells at a rate determined by the leakiest cell in the device. However, most DRAM cells can retain data for significantly longer. Therefore, many of these refreshes are unnecessary. In this paper, we propose RAIDR (Retention-Aware Intelligent DRAM Refresh), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times. Our key idea is to group DRAM rows into retention time bins and apply a different refresh rate to each bin. As a result, rows containing leaky cells are refreshed as frequently as normal, while most rows are refreshed less frequently. RAIDR uses Bloom filters to efficiently implement retention time bins. RAIDR requires no modification to DRAM and minimal modification to the memory controller. In an 8-core system with 32 GB DRAM, RAIDR achieves a 74.6% refresh reduction, an average DRAM power reduction of 16.1%, and an average system performance improvement of 8.6% over existing systems, at a modest storage overhead of 1.25 KB in the memory controller. RAIDR's benefits are robust to variation in DRAM system configuration, and increase as memory capacity increases.
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Cites
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Die Stacking (3D) Microarchitecture
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Overcoming the challenges of crossbar resistive memory architectures
Xu, C., Niu, D., Muralimanohar, N., Balasubramonian, R., Zhang, T., Yu, S., & Xie, Y. (2015) · 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2015.7056056 · Cited by 340
Liu, J., Jaiyen, B., Kim, Y., Wilkerson, C., & Mutlu, O. (2013) · Proceedings of the 40th Annual International Symposium on Computer Architecture · doi:10.1145/2485922.2485928 · Cited by 279
Self-citationA survey of architectural techniques for DRAM power management
Mittal, S. (2012) · International Journal of High Performance Systems Architecture · doi:10.1504/ijhpsa.2012.050990 · Cited by 46
Processing data where it makes sense in modern computing systems: Enabling in-memory computation
Mutlu, O. (2018) · 2018 7th Mediterranean Conference on Embedded Computing (MECO) · doi:10.1109/meco.2018.8405955 · Cited by 30
Self-citation
Metadata
- Authors
- Liu, J., Jaiyen, B., Veras, R., & Mutlu, O.
- Venue
- ACM SIGARCH Computer Architecture News
- Published
- 2012-09-05
- Volume
- 40
- Issue
- 3
- Pages
- 1-12
- ISSN
- 0163-5964 (ISSN-L)
- OpenAlex
- W2119092821
- Cited by
- 444
- References
- 27
- FWCI
- 53.35
- Type
- journal article
- Language
- en
- Open access
- closed
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