Cited by 341Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance DevicesDNA and Biological Computing

Spike-timing-dependent learning in memristive nanodevices

Snider, Greg S.·2008·2008 IEEE International Symposium on Nanoscale Architectures

Abstract

The neuromorphic paradigm is attractive for nanoscale computation because of its massive parallelism, potential scalability, and inherent defect-, fault-, and failure-tolerance. We show how to implement timing-based learning laws, such as spike-timing-dependent plasticity (STDP), in simple, memristive nanodevices, such as those constructed from certain metal oxides. Such nano-scale ldquosynapsesrdquo can be combined with CMOS ldquoneuronsrdquo to create neuromorphic hardware several orders of magnitude denser than is possible in conventional CMOS. The key ideas are: (1) to factor out two synaptic state variables to pre- and post-synaptic neurons; and (2) to separate computational communication from learning by time-division multiplexing of pulse-width-modulated signals through synapses. This approach offers the advantages of: better control over power dissipation; fewer constraints on the design of memristive materials used for nanoscale synapses; learning dynamics can be dynamically turned on or off (e.g. by attentional priming mechanisms communicated extra-synaptically); greater control over the precise form and timing of the STDP equations; the ability to implement a variety of other learning laws besides STDP; better circuit diversity since the approach allows different learning laws to be implemented in different areas of a single chip using the same memristive material for all synapses.

Integrity signals

Registry

Crossref · 10.1109/nanoarch.2008.4585796

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22 of 22 references verified0 citation errors · 0 not checkable

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  • Memristors can be used to implement digital logic, synapses in neural applications, and hybrid circuits.

    “They can also be used to implement digital logic [9], synapses in neural applications [10,11], and hybrid circuits [6,12].”

    From Sub-nanosecond switching of a tantalum oxide memristor (2011) · cites this paper as [10]

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Authors
Snider, G. S.
Affiliations
Hewlett-Packard (United States) (US)
Corresponding author
Snider, Greg S.
Venue
2008 IEEE International Symposium on Nanoscale Architectures
Publisher
IEEE
Published
2008-06
Pages
85-92
OpenAlex
W2101834447
Cited by
341
References
22
Citations by year
2026: 4 · 2025: 3 · 2024: 8 · 2023: 9 · 2022: 12 · 2021: 11 · 2020: 12 · 2019: 19 · 2018: 14 · 2017: 24 · 2016: 17 · 2015: 30 · 2014: 24 · 2013: 46 · 2012: 43
FWCI
30.31
Type
conference paper
Language
en
Open access
closed
Locations
IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (publishedVersion)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
  • Life Sciences › Biochemistry, Genetics and Molecular Biology › Molecular Biology › DNA and Biological Computing
Keywords
spike-timing-dependent plasticity, neuromorphic hardware, time-division multiplexing, pulse width modulation, power dissipation, learning law, attentional priming, fault-tolerant computing

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