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Spike-timing-dependent learning in memristive nanodevices
Abstract
The neuromorphic paradigm is attractive for nanoscale computation because of its massive parallelism, potential scalability, and inherent defect-, fault-, and failure-tolerance. We show how to implement timing-based learning laws, such as spike-timing-dependent plasticity (STDP), in simple, memristive nanodevices, such as those constructed from certain metal oxides. Such nano-scale ldquosynapsesrdquo can be combined with CMOS ldquoneuronsrdquo to create neuromorphic hardware several orders of magnitude denser than is possible in conventional CMOS. The key ideas are: (1) to factor out two synaptic state variables to pre- and post-synaptic neurons; and (2) to separate computational communication from learning by time-division multiplexing of pulse-width-modulated signals through synapses. This approach offers the advantages of: better control over power dissipation; fewer constraints on the design of memristive materials used for nanoscale synapses; learning dynamics can be dynamically turned on or off (e.g. by attentional priming mechanisms communicated extra-synaptically); greater control over the precise form and timing of the STDP equations; the ability to implement a variety of other learning laws besides STDP; better circuit diversity since the approach allows different learning laws to be implemented in different areas of a single chip using the same memristive material for all synapses.
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“They can also be used to implement digital logic [9], synapses in neural applications [10,11], and hybrid circuits [6,12].”
From Sub-nanosecond switching of a tantalum oxide memristor (2011) · cites this paper as [10]
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BackgroundInfluentialSynaptic behaviors of a single metal–oxide–metal resistive device
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“An implementation of a different learning law, spike-timing-dependent plasticity (STDP), using memristive nanode-vices was proposed by Snider (2008) and implemented with a single memristive device by Jo et al (2010).”
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Implementation of memristive neural networks with spike-rate-dependent plasticity synapses
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BackgroundMemristive and Memory Impedance Behavior in a Photo-Annealed ZnO–rGO Thin-Film Device
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“This trend is reinforced with the latest proposals to use memristive nanodevices as synapses, which are particularly attractive to implement efficient timing-based learning rules like Spike-TimingDependent Plasticity (STDP) in dense crossbar arrays [5]–[9].”
MethodNeuromorphic Processors with Memristive Synapses
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BackgroundA VDTA-based robust electronically tunable memristor emulator circuit
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“The spike can be approximated by either a continuous (Afifi et al., 2009; Linares-Barranco and Serrano-Gotarredona, 2009) or discrete (Jo et al., 2010; Snider, 2008) waveform through time, which is transmitted to all synapses that the neuron is connected to (presynaptic or postsynaptic).”
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Insect-inspired neuromorphic computing
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Ali, S., Ullah, M. A., Raza, A., Iqbal, M. W., Khan, M. F., Rasheed, M., Ismail, M., & Kim, S. (2023) · Nanomaterials · doi:10.3390/nano13172443 · Cited by 22
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“Most notably, Snider [3] showed the concept of using memristive memories to implement the Spike Timing Dependent Plasticity (STDP) learning rule, by virtue of their own physics.”
BackgroundInfluentialFerroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture
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“In neurobiologically realistic learning schemes the synaptic connections of a network are tuned by time-encoded spike-like signals (Snider, 2008), which typically requires nonlinear memristive device characteristics in a time-dependent manner (Ziegler et al., 2015; Dittmann and Strachan, 2019).”
BackgroundMemristor: Models, Types, and Applications
Radwan, A. G., & Fouda, M. E. (2015) · Studies in systems, decision and control · doi:10.1007/978-3-319-17491-4_2 · Cited by 20
Design of adaptive nano/CMOS neural architectures
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“Synchronous multi-phase memristive STDP learning architectures have been proposed in the literature [18].”
BackgroundDynamical properties of electrical circuits with fully nonlinear memristors
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A CMOS-memristive self-learning neural network for pattern classification applications
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BackgroundMethodDesign and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices
Liao, S.-Y., Retrouvey, J.-M., Agnus, G., Zhao, W. S., Maneux, C., Frégonèse, S., Zimmer, T., Chabi, D., Filoramo, A., Derycke, V., et al. (2011) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2011.2112590 · Cited by 17
“design: i) It allows parallel learning [19], therefore greatly improving the learning speed, which is a strong limitation in conventional neuromorphic circuits based on serial learning [17], [20].”
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“Experimental [79, 80] and theoretical [81, 82] studies have explored how the plasticity dynamics of memristors can be utilized in spiking neural networks.”
BackgroundMemristors and Memristive Devices for Neuromorphic Computing
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“Previously proposed solutions involve pulse width or height modulation or pulse shaping [4-6] and would require extensive auxiliary circuitry.”
Towards evolving spiking networks with memristive synapses
Howard, G., Gale, E., Bull, L., Costello, B. D. L., & Adamatzky, A. (2011) · IEEE Symposium on Artificial Life (ALIFE) · doi:10.1109/alife.2011.5954655 · Cited by 16
“Previous studies have presented methods to implement STDP learning using memristive synapses, notably [23-26].”
MethodMemristor synaptic dynamics' influence on synchronous behavior of two Hindmarsh-Rose neurons
Corinto, F., Ascoli, A., Lanza, V., & Gilli, M. (2011) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2011.6033530 · Cited by 16
“Recently, it was experimentally proved that hybrid synapse/neuron networks made up of complementary metaloxide-semiconductor (CMOS) neurons and nanoscale memristor synapses are able to support spike-timing-dependent plasticity, an important synaptic adaptation rule for competitive Hebbian learning ([5], [6], [7]).”
BackgroundAn a VLSI driving circuit for memristor-based STDP
Acciarito, S., Cristini, A., Nunzio, L. D., Khanal, G. M., & Susi, G. (2016) · Conference on Ph.D. Research in Microelectronics and Electronics · doi:10.1109/prime.2016.7519503 · Cited by 15
“In recent years, memristor has been exploited for emulating STDP behavior in neuromorphic systems [9]–[12].”
BackgroundOn-Chip Universal Supervised Learning Methods for Neuro-Inspired Block of Memristive Nanodevices
Chabi, D., Zhao, W. S., Querlioz, D., & Klein, J. (2015) · ACM Journal on Emerging Technologies in Computing Systems · doi:10.1145/2629503 · Cited by 14
“Several techniques focus on unsupervised learning methods, based on the imitation of Spike Timing Dependent Plasticity, a biological learning rule [Jo et al. 2010; Snider 2008; P´erez-Carrasco et al. 2010; Querlioz et al. 2011a] or the instar/outstar learning rule [Snider 2011] .”
MethodEfficient Hybrid CMOS-Nano Circuit Design for Spiking Neurons and Memristive Synapses with STDP
Afifi, A., Ayatollahi, A., Raissi, F., & Hajghassem, H. (2010) · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · doi:10.1587/transfun.e93.a.1670 · Cited by 15
Memristor based STDP learning network for position detection
Ebong, I. E., & Mazumder, P. (2010) · doi:10.1109/icm.2010.5696142 · Cited by 15
“been proposed[ 7 ]. In their current state, they do not provide”
BackgroundA Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems
Adnan, M. M., Sayyaparaju, S., Rose, G. S., Schuman, C. D., Ku, B. W., & Lim, S. K. (2018) · IEEE International System-on-Chip Conference (SOCC) · doi:10.1109/socc.2018.8618553 · Cited by 15
“This property enables it to be used as a synapse in CMOS-memristor hybrid circuits [3].”
MethodLone, A. H., Amara, S., & Fariborzi, H. (2022) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/ac57a2 · Cited by 14
“To address these problems, researchers are working at different levels of abstractions such as novel materials and devices [3, 4], and new architectures such as neuromorphic computing [5, 6].”
BackgroundAli, S., Khan, M. F., Ullah, M. A., & Iqbal, M. W. (2025) · Journal of Alloys and Compounds · doi:10.1016/j.jallcom.2025.178800 · Cited by 15
Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic Systems
Sayyaparaju, S., Chakma, G., Amer, S., & Rose, G. S. (2017) · ACM Great Lakes Symposium on VLSI (GLSVLSI) · doi:10.1145/3060403.3060418 · Cited by 14
“Online learning is often based on unsupervised learning such as Spike Time Dependent Plasticity (STDP), Long Term Po-tentiation (LTP), and Long Term Depression (LTD) [9,10].”
BackgroundInfluentialDesign of a Robust Memristive Spiking Neuromorphic System with Unsupervised Learning in Hardware
Adnan, M. M., Sayyaparaju, S., Brown, S. D., Shawkat, M. S. A., Schuman, C. D., & Rose, G. S. (2021) · ACM Journal on Emerging Technologies in Computing Systems · doi:10.1145/3451210 · Cited by 14
Analog memristive time dependent learning using discrete nanoscale RRAM devices
Singha, A., Muralidharan, B., & Rajendran, B. (2014) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2014.6889915 · Cited by 14
“While most of the fabricated memristive devices show an on-off conductance ratio greater than 100 [4], we particularly tune or choose our pre-synaptic and post-synaptic programming pulses to partially switch our analog device so that the modified on-off ratio is within a range of approximately 2,…”
BackgroundSPICE simulation of nanoscale non-crystalline silicon TFTs in spiking neuron circuits
Cantley, K. D., Subramaniam, A., Stiegler, H. J., Chapman, R. A., & Vogel, E. M. (2010) · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · doi:10.1109/mwscas.2010.5548881 · Cited by 14
Memristive fuzzy edge detector
Merrikh-Bayat, F., Shouraki, S. B., & Merrikh‐Bayat, F. (2012) · Journal of Real-Time Image Processing · doi:10.1007/s11554-012-0254-9 · Cited by 14
“ture to store the 2-dimensional analog weight matrix of a neural network [16, 17].”
BackgroundFoglietti, V., Yang, N. Q., Aruta, C., Pietrantonio, F. D., Cannatà, D., Benetti, M., & Balestrino, G. (2016) · Nanotechnology · doi:10.1088/0957-4484/27/37/375705 · Cited by 14
CMOL implementation of spiking neurons and spike-timing dependent plasticity
Afifi, A., Ayatollahi, A., & Raissi, F. (2011) · International Journal of Circuit Theory and Applications · doi:10.1002/cta.638 · Cited by 13
“Using a non-flexible but a practical version of CMOL architecture which uses ‘memristive’ nanodevices in place of molecular switches, Snider has proposed a self-organized computation [2] and STDP learning [17] with continuous weight synapse in a synchronous paradigm.”
MethodSynaptic behaviors of HfO2 ReRAM by pulse frequency modulation
Lee, D. K., Kim, M., Kim, T., Bang, S., Choi, Y.-J., Kim, S., Cho, S., & Park, B. (2019) · Solid-State Electronics · doi:10.1016/j.sse.2019.02.008 · Cited by 13
Soltiz, M., Merkel, C. E., Kudithipudi, D., & Rose, G. S. (2012) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1145/2765491.2765530 · Cited by 13
Yakopcic, C., Taha, T. M., Subramanyam, G., Shin, E., Murray, P. T., & Rogers, S. (2010) · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · doi:10.1117/12.861513 · Cited by 13
“These features suggest that the memristor can be used to model a system similar to the synaptic response in brain tissue [2].”
MethodCompact floating-gate learning array with STDP
Pänkäälä, M., Laiho, M., & Hasler, P. E. (2009) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2009.5178879 · Cited by 13
“The approach uses pulse width modulation and the modification of weights takes place within several time frames.”
BackgroundMethodMathematical models and circuit implementations of memristive systems
Corinto, F., Ascoli, A., & Gilli, M. (2012) · International Workshop on Cellular Nanoscale Networks and their Applications (CNNA) · doi:10.1109/cnna.2012.6331458 · Cited by 12
“This discovery opened novel attractive opportunities in integrated circuit (IC) design, particularly for the realization of innovative non-volatile memories [18] and pioneering neuromorphic systems [5].”
BackgroundSynaptic weighting circuits for Cellular Neural Networks
Kim, Y., & Min, K. (2012) · International Workshop on Cellular Nanoscale Networks and their Applications (CNNA) · doi:10.1109/cnna.2012.6331430 · Cited by 12
“One of key advantages of neural network systems is that massive parallelism can be more easily implementable thus the energy efficiency of neural network systems can be better than the conventional von Neumann systems that have been the theoretical ground for the modern high-speed digital systems longer than last 50 y…”
BackgroundRoclin, D., Bichler, O., Gamrat, C., Thorpe, S. J., & Klein, J. (2013) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2013.6707071 · Cited by 12
“For an analog SNN, where a synapse could be implemented by a single memristor [9]–[11], this study will help determine the minimum number of resistance levels a memristor would require for such applications.”
BackgroundMethodComparison of the Performance of the Memristor Models in 2D Cellular Nonlinear Network
Isah, A., Nguetcho, A. S. T., Binczak, S., & Bilbault, J. (2021) · Electronics · doi:10.3390/electronics10131577 · Cited by 12
Study of Synaptic Behavior in Doped Transition Metal Oxide-Based Reconfigurable Devices
Mandal, S., Long, B., & Jha, R. (2013) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2013.2288327 · Cited by 12
Suarez, L. E., Kendall, J. D., & Nino, J. C. (2018) · Neural Networks · doi:10.1016/j.neunet.2018.07.003 · Cited by 12
Quick noise-tolerant learning in a multi-layer memristive neural network
Chen, L., Li, C., Huang, T., & Wang, X. (2013) · Neurocomputing · doi:10.1016/j.neucom.2013.05.043 · Cited by 11
Kim, J., Cho, S., Kim, T., & Pak, J. J. (2019) · Journal of Electrical Engineering and Technology · doi:10.1007/s42835-019-00107-y · Cited by 11
Evolving unipolar memristor spiking neural networks
Howard, D., Bull, L., & Costello, B. D. L. (2015) · Connection Science · doi:10.1080/09540091.2015.1080225 · Cited by 12
“A string of publications from the group of Stefano Fusi focuses on the how the number of available synaptic resistance states affects memory and learning in neural networks e.g., [11], [12].”
Background
Metadata
- Authors
- Snider, G. S.
- Affiliations
- Hewlett-Packard (United States) (US)
- Corresponding author
- Snider, Greg S.
- Venue
- 2008 IEEE International Symposium on Nanoscale Architectures
- Publisher
- IEEE
- Published
- 2008-06
- Pages
- 85-92
- OpenAlex
- W2101834447
- Cited by
- 341
- References
- 22
- Citations by year
- 2026: 4 · 2025: 3 · 2024: 8 · 2023: 9 · 2022: 12 · 2021: 11 · 2020: 12 · 2019: 19 · 2018: 14 · 2017: 24 · 2016: 17 · 2015: 30 · 2014: 24 · 2013: 46 · 2012: 43
- FWCI
- 30.31
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Mathematics › Theoretical Computer Science › DNA and Biological Computing
- Keywords
- spike-timing-dependent plasticity, neuromorphic hardware, time-division multiplexing, pulse width modulation, power dissipation, learning law, attentional priming, fault-tolerant computing
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