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An Effective Current Balancing Method for Inverters With Paralleled Silicon Carbide Power Modules
Open accessAbstract
Silicon carbide (SiC) MOSFET has many superior characteristics in high power applications. Paralleling the SiC devices is an effective approach to increase the current capacity of the system, which also leads to current sharing issues. In this article, both transient and steady-state current sharing issues are studied for the high-power grid-tied inverters with paralleled SiC modules with an effective current balancing strategy proposed to address both issues simultaneously. The steady-state imbalance current due to the parameter mismatch is suppressed by the self-inductance of power cables used for paralleling connection. With the elimination of steady-state imbalance current, the transient imbalance current sensing is much simplified and can be realized by using low-cost current sensors. With the sensed imbalance current, a closed-loop control approach is proposed to adjust the modulation reference signal for each module to mitigate the remaining transient imbalance current. The proposed method is straightforward to implement with enhanced compatibility and flexibility compared to existing methods. Experimental studies are performed using inverters with 2 and 4 power modules paralleled in each phase to demonstrate the effectiveness of the proposed method.
Overview
CoChat Summary
TL;DR
This paper proposes a hybrid current-balancing method for grid-tied inverters with paralleled SiC power modules, using power-cable inductance to suppress steady-state imbalance from parameter mismatch and closed-loop PWM edge tuning to reduce remaining transient imbalance. Experiments with 2 and 4 paralleled modules per phase show improved current sharing and more even loss distribution.
Key findings
- The proposed method decouples steady-state and transient imbalance: cable/inserted inductance suppresses steady-state imbalance caused by Rds_on mismatch, while closed-loop PWM edge tuning compensates the remaining transient imbalance caused mainly by Vth mismatch.
- In simulation, inserted inductors of 5 µH in a clamped inductive load and 30 µH in a three-phase inverter reduced steady-state current spikes; a steady-state current-difference change ratio ρ reaches 5% at Lins = 28 µH, described as a cost-effective value for simplified sensing.
- Experimental tests used power cables with 35 µH self-inductance each; without PWM edge tuning, steady-state current spikes disappeared, and with PWM edge tuning the paralleled currents were further balanced for both 2-module and 4-module-per-phase inverters.
- Calculated MOSFET losses for the 4-module hard-parallel case showed total-loss mismatches of 41.4% for top and 35% for bottom switches; with cable connection and PWM edge tuning, these mismatches were reduced to 9.3% and 11.3%, respectively.
Methods
- The paper analyzes transient and steady-state imbalance causes, then validates with LTspice simulations of a clamped inductive load and a three-phase inverter with paralleled MOSFETs; Vth and Rds_on of the second device/module are set 30% higher than the first, with inserted inductors of 5 µH in the CIL study and 30 µH in the inverter simulation.
- Experimental verification uses a three-phase inverter with Wolfspeed CAB450M12XM3 SiC modules, with 2 and 4 modules paralleled in each phase; the load is inductive with 180 µH phase inductance, SPWM uses a 400 Hz reference, DC bus is 500 V, switching frequency is 10 kHz, and the dSPACE MicroLabBox has 10 ns PWM resolution.
- Current feedback uses LEM LA 150-P sensors with 150 kHz bandwidth; a PI controller adjusts the modulation reference of non-reference paralleling branches based on sensed current difference, and power cables provide about 35 µH self-inductance per branch.
Limitations
- Stated: the inserted cable-inductance approach may not be suitable for applications requiring high power density, though the paper argues long power cables are common in grid-tied inverter applications.
- Stated: the method relies on appropriate cable self-inductance, which can be estimated from cable length and diameter, and same cables are needed to keep paralleled-branch inductances within a small tolerance.
- Evident from the text: validation is limited to laboratory inverters with 2 and 4 paralleled modules, 500 V DC bus, 10 kHz switching, and an inductive load; the paper does not report long-term thermal, EMI, or reliability data beyond calculated loss distribution.
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Claims the paper makes
34 Own interpretation · 26 Own result · 6 No full text of the sources · 6 Not checked yet
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“As a result, the four currents are balanced as can be seen from Fig. 28.”
§ An Effective Current Balancing Method for Inverters with Paralleled Silicon Carbide Power Modules > B. Inverter with Four Modules Paralleled in Each Phase
plainstates a causeSingle case- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: passes — The paper’s conclusions depend on it.
- Based: passes — The paper gives a reason why it holds.
- Rests on an assumption not shown here.
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“Fig. 22(a) shows the transition of enabling PWM tuning, which shows a good imbalance current suppression response when the closed-loop controller is enabled, as represented by the blue curve.”
§ An Effective Current Balancing Method for Inverters with Paralleled Silicon Carbide Power Modules > C. Closed-loop Control for Imbalance Current Suppression with PWM Edge Tuning
plainstates a causeSingle case- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: passes — The paper’s conclusions depend on it.
- Based: passes — The paper gives a reason why it holds.
- Rests on an assumption not shown here.
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“However, the imbalance current caused by transient parameter mismatch still exists in Fig. 27.”
§ An Effective Current Balancing Method for Inverters with Paralleled Silicon Carbide Power Modules > B. Inverter with Four Modules Paralleled in Each Phase
plainSingle case- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: passes — The paper’s conclusions depend on it.
- Based: passes — The paper gives a reason why it holds.
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“Fig. 13(b) shows that the two current waveforms have the same slopes with the inserted cable inductance.”
§ An Effective Current Balancing Method for Inverters with Paralleled Silicon Carbide Power Modules > A. Impact of Parameter Mismatches at Inverter System Level
plainstates a cause- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: passes — The paper’s conclusions depend on it.
- Based: passes — The paper gives a reason why it holds.
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“Compared with waveforms in Fig. 6, the steady state current difference caused by Rds_on mismatch has been mitigated since the two currents are paralleling with each other during the steady state.”
§ An Effective Current Balancing Method for Inverters with Paralleled Silicon Carbide Power Modules > A. Compound Effect of both Transient and Steady-state Parameters Mismatches
plainstates a cause- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: passes — The paper’s conclusions depend on it.
- Based: passes — The paper gives a reason why it holds.
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Self-check
Percentages, sums and reported differences re-computed from the paper’s own numbers.
Each contradiction between two passages listed here was confirmed by an independent check.
Rated minor: it would not touch a result — a value no result rests on, a p-value that stays on the same side of the significance level, or a conflict that is clerical, resolved elsewhere in the paper, or outside its own findings.
In the paper
§ An Effective Current Balancing Method for Inverters with Paralleled Silicon Carbide Power Modules > A. Impact of Parameter Mismatches at Inverter System Level
“Simulation waveforms of the inverter with inserted equivalent cable inductors are shown in Fig. 12.”
§ An Effective Current Balancing Method for Inverters with Paralleled Silicon Carbide Power Modules > B. Inverter with Four Modules Paralleled in Each Phase
“Fig. 12. Schematic of the inverter with equivalent cable inductors.”
Citations
Cites
Review of Silicon Carbide Power Devices and Their Applications
She, X., Huang, A. Q., Lucia, O., & Ozpineci, B. (2017) · IEEE Transactions on Industrial Electronics · doi:10.1109/tie.2017.2652401 · Cited by 1,773
(1991) · CERN Document Server (European Organization for Nuclear Research) · Cited by 1,028
Wang, J., Chung, H. S.-H., & Li, R. T.-H. (2012) · IEEE Transactions on Power Electronics · doi:10.1109/tpel.2012.2195332 · Cited by 573
Influences of Device and Circuit Mismatches on Paralleling Silicon Carbide MOSFETs
Li, H., Munk-Nielsen, S., Wang, X., Maheshwari, R., Beczkowski, S., Uhrenfeldt, C., & Franke, W.-T. (2016) · IEEE Transactions on Power Electronics · doi:10.1109/tpel.2015.2408054 · Cited by 306
Zeng, Z., Zhang, X., & Zhang, Z. (2020) · IEEE Transactions on Industrial Electronics · doi:10.1109/tie.2019.2901655 · Cited by 161
Zhao, C., Wang, L., & Zhang, F. (2020) · IEEE Transactions on Power Electronics · doi:10.1109/tpel.2019.2954716 · Cited by 146
Wen, Y., Yang, Y., & Gao, Y. (2021) · IEEE Transactions on Power Electronics · doi:10.1109/tpel.2020.3006071 · Cited by 144
Bortis, D., Biela, J., & Kolar, J. W. (2008) · IEEE Transactions on Plasma Science · doi:10.1109/tps.2008.2003971 · Cited by 127
A Novel DBC Layout for Current Imbalance Mitigation in SiC MOSFET Multichip Power Modules
Li, H., Munk‐Nielsen, S., Bęczkowski, S., & Wang, X. (2016) · IEEE Transactions on Power Electronics · doi:10.1109/tpel.2016.2562030 · Cited by 117
Mao, Y., Miao, Z., Wang, C., & Ngo, K. D. T. (2017) · IEEE Transactions on Industrial Electronics · doi:10.1109/tie.2017.2716868 · Cited by 111
Research works printed but not linked: 1
- Stevanovic, From SiC MOSFET devices to MW-scale power converters
Cited by
Cao, H., Lin, N., Darvish, P., Yang, Y., Wang, Z., & Zhao, Y. (2024) · Conference proceedings/Conference proceedings - IEEE Applied Power Electronics Conference and Exposition · doi:10.1109/apec48139.2024.10509031 · Cited by 14
Self-citationHe, Y. (2024) · CPSS Transactions on Power Electronics and Applications · doi:10.24295/cpsstpea.2024.00004 · Cited by 10
Parker, M., Neira, S., Horsley, E. L., Finney, S. J., & Judge, P. D. (2024) · IEEE Transactions on Power Electronics · doi:10.1109/tpel.2024.3453438 · Cited by 10
Tang, T., Song, W., Chen, J., Hu, T., Yue, H., & Liu, G. (2025) · IEEE Transactions on Power Electronics · doi:10.1109/tpel.2025.3585668 · Cited by 4
RMS Current Balancing of Parallel SiC Bridge Arms Based on a Rotational Rest Control Strategy
Song, R., Chen, G., Zhang, Z., & Li, Z. (2025) · IEEE Transactions on Power Electronics · doi:10.1109/tpel.2025.3625306 · Cited by 1
Metadata
- Authors
- Lin, N., Zhao, Y., & Mantooth, H. A.
- Affiliations
- University of Arkansas at Fayetteville (US)
- Venue
- IEEE Transactions on Industry Applications
- Published
- 2023-11
- Volume
- 59
- Issue
- 6
- Pages
- 6986-7000
- ISSN
- 0093-9994 (ISSN-L)
- 1939-9367
- OpenAlex
- W4385976105
- Cited by
- 13
- References
- 27
- Citations by year
- 2026: 3 · 2025: 5 · 2024: 5
- FWCI
- 0.93
- Type
- journal article
- Language
- en
- Open access
- green
- www.osti.gov
- Licence
- Locations
- IEEE Transactions on Industry Applications (publishedVersion)
- OSTI OAI (U.S. Department of Energy Office of Scientific and Technical Information) (submittedVersion)
- Funders
- Advanced Research Projects Agency - Energy
- U.S. Department of Energy (DE-AR0000895, DE-EE0006521)
- Office of Energy Efficiency and Renewable Energy
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Silicon Carbide Semiconductor Technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Multilevel Inverters and Converters
- Physical Sciences › Engineering › Control and Systems Engineering › Microgrid Control and Optimization
- Keywords
- SiC MOSFET, current balancing, current sharing, grid-connected inverter, parameter mismatch, feedback control
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