Student or educator? Sign up with your school email and get 6 months of Pro free.
CoChat
Sign Up
Cited by 135Silicon Carbide Semiconductor TechnologiesAdvanced DC-DC ConvertersMultilevel Inverters and Converters

The DOI matches its Crossref record; 120 of the 121 references it cites were found in a registry or an index; none of the 79 sources its claims cite is checked for support yet.

Parallel Connection of Silicon Carbide MOSFETs—Challenges, Mechanism, and Solutions

Open access
Li, Helong, Zhao, Shuang, Wang, Xiongfei, Ding, Lijian, Mantooth, Homer Alan·2023·IEEE Transactions on Power Electronics
DOI 10.1109/tpel.2023.3278270
Open this paper in CoChat — free accountOpen PDF

Abstract

Power semiconductor devices are often connected in parallel to increase the current rating of the power conversion systems. However, due to mismatched circuit parameters or semiconductor fabrication discrepancies, the current of paralleled power semiconductor devices can be unbalanced, which potentially leads to accelerated aging and long-term reliability issues. The fast-switching speed of silicon carbide (SiC) devices aggravates this problem due to its higher sensitivity to parasitic parameters. Numerous efforts have been dedicated to analyzing and addressing the current imbalance issue of paralleling SiC devices. This article comprehensively summarizes and presents state-of-the-art research regarding the current imbalance in paralleled SiC devices. Degree of imbalance is proposed to comprehensively quantify the current mismatch. Starting with mechanism analysis, different types of current imbalance are categorized. Various device parameters and the package layout that impact the current distribution are investigated. The existing solutions including passive methods and active methods are concluded and categorized. This work also incorporates insight into the future development needs of high-power multichip SiC module packaging and driving technologies.

Overview

CoChat Summary

TL;DR

This review synthesizes the mechanisms and mitigation of current imbalance in paralleled SiC MOSFETs, proposing static and dynamic Degree of Imbalance (DoI) metrics. It categorizes causes into device parameters, circuit parasitics, and status indicators, and reviews passive and active current-sharing solutions.

Key findings

  • Paralleling SiC MOSFETs is more challenging than paralleling Si IGBTs due to smaller dies, larger parameter spread, and faster switching. On a 6-inch wafer, yield falls from 97.54% for 5 × 5 mm dies to 90.56% for 10 × 10 mm dies; for ≤750 V, a single SiC die is about 100 A at 5 × 5 mm² versus about 300 A at 10 × 12 mm² for Si IGBT.
  • Static imbalance is mainly from \(R_{dson}\) mismatch, while dynamic imbalance arises from \(V_{th}\), \(L_s\), gate delay, and related factors. \(R_{dson}\)’s positive temperature coefficient self-balances static current, but \(V_{th}\)’s negative temperature coefficient can self-aggravate and risk thermal runaway. For 650 V SiC, \(R_{CH}\) can exceed 50% of total \(R_{dson}\); for 1.7 kV, it can be below 30%.
  • \(L_s\) mismatch strongly affects dynamic current sharing; \(L_d\) has little dynamic impact but affects ringing and can affect static sharing if current changes; \(L_g\) mismatch is minor. An auxiliary source connection reduced peak current difference from 18 A to 9 A in a four-die module.
  • Solutions are passive (die preselection/screening, symmetric layout) and active (external passive components, active gate drivers). Design rules are to reduce mismatched \(L_s\) and the \(di/dt\) applied across it. AGD is challenging because SiC transients can be within 100 ns, with \(di/dt\) up to 5 A/ns and \(dV/dt\) over 50 V/ns.

Methods

  • Review/synthesis of state-of-the-art research on paralleling SiC MOSFETs; proposes static and dynamic DoI indices and categorizes pertinent parameters into device, circuit, and status types.
  • Draws on cited experimental and simulation evidence, including curve-tracer testing of 20 SiC MOSFETs for \(V_{th}\), LTspice simulation for \(L_g\), PFC converter simulation for \(T_j\), and module current-sharing experiments.

Limitations

  • The paper does not state limitations of the review itself.
  • Evident from the text: as a review, it synthesizes prior work rather than providing a systematic meta-analysis or unified experimental validation across all methods.
  • The paper notes technology limitations: AGD is premature for SiC due to very short switching transients (often within 100 ns; \(di/dt\) up to 5 A/ns), external passive components add cost and parasitics, and high-temperature known-good-die (KGD) for mass production remains challenging.

Model-written summary. Check it against the paper before relying on it.

Integrity signals

Registry

Crossref · 10.1109/tpel.2023.3278270

Cites

120 of 120 references verified0 citation errors · 0 not checkable

Statistics

Nothing to recompute.

Figures

Fig. 1 IGBT-high-current-module with paralleled IGBTs and diodes.
Fig. 1 IGBT-high-current-module with paralleled IGBTs and diodes.CC-BY · From the PDF
Fig. 2 6-inch wafer for the dies under different sizes. (a) 5 × 5 mm die size. (b) 10 × 10 mm die size.
Fig. 2 6-inch wafer for the dies under different sizes. (a) 5 × 5 mm die size. (b) 10 × 10 mm die size.CC-BY · From the PDF
Image 3
CC-BY · From the PDF
Fig. 4 Thermal performance with different distances among paralleled dies.
Fig. 4 Thermal performance with different distances among paralleled dies.CC-BY · From the PDF
Fig. 5 Experimental waveform of steady-state current imbalance.
Fig. 5 Experimental waveform of steady-state current imbalance.CC-BY · From the PDF
Fig. 6 Turn-ON process of the two special cases of parallel-connected MOSFETS. (a) Asynchronous gate signal and same switching slew rate. (b) Synchronous gate signal and different slew rate [47].
Fig. 6 Turn-ON process of the two special cases of parallel-connected MOSFETS. (a) Asynchronous gate signal and same switching slew rate. (b) Synchronous gate signal and different slew rate [47].CC-BY · From the PDF
Fig. 7 Turn-OFF process of the two parallel-connected MOSFETs [47].
Fig. 7 Turn-OFF process of the two parallel-connected MOSFETs [47].CC-BY · From the PDF
Image 8
CC-BY · From the PDF
Fig. 9 Thermal network of a bottom-side cooling power device [1].
Fig. 9 Thermal network of a bottom-side cooling power device [1].CC-BY · From the PDF
Fig. 10 T j profile of paralleled SiC MOSFETs in a PFC.
Fig. 10 T j profile of paralleled SiC MOSFETs in a PFC.CC-BY · From the PDF
Fig. 11 Relationship between the number of life cycles and junction temperature.
Fig. 11 Relationship between the number of life cycles and junction temperature.CC-BY · From the PDF
Fig. 12 Equivalent circuit of the parallel-connected power devices.
Fig. 12 Equivalent circuit of the parallel-connected power devices.CC-BY · From the PDF
TABLE I TYPICAL PARAMETERS THAT AFFECT THE CURRENT DISTRIBUTION ON PARALLEL-CONNECTED MOSFET
TABLE I TYPICAL PARAMETERS THAT AFFECT THE CURRENT DISTRIBUTION ON PARALLEL-CONNECTED MOSFETCC-BY · From the PDF
Fig. 14 Normalized R dson versus virtual junction temperature.
Fig. 14 Normalized R dson versus virtual junction temperature.CC-BY · From the PDF
Fig. 15 V th of multiple SiC MOSFETs.
Fig. 15 V th of multiple SiC MOSFETs.CC-BY · From the PDF
Image 16
CC-BY · From the PDF
Image 17
CC-BY · From the PDF
Fig. 18 ON-state equivalent circuit of paralleling two SiC MOSFETs.
Fig. 18 ON-state equivalent circuit of paralleling two SiC MOSFETs.CC-BY · From the PDF
Fig. 19 Experimental current sharing performance of M1 and M4 ( L s4 > L s1 ). (a) Turn-ON waveform. (b) Turn-OFF waveform.
Fig. 19 Experimental current sharing performance of M1 and M4 ( L s4 > L s1 ). (a) Turn-ON waveform. (b) Turn-OFF waveform.CC-BY · From the PDF
Fig. 20 LTspice Simulation waveform with the impact of L g on turn-ON transient.
Fig. 20 LTspice Simulation waveform with the impact of L g on turn-ON transient.CC-BY · From the PDF
Image 21
CC-BY · From the PDF
Fig. 22 Simulation result of current waveform of four paralleled MOSFETs. (a) With current coupling effects. (b) Without current coupling effects.
Fig. 22 Simulation result of current waveform of four paralleled MOSFETs. (a) With current coupling effects. (b) Without current coupling effects.CC-BY · From the PDF
Fig. 23 Power module layout with paralleling half-bridge configurations. (a) Package layout. (b) Bus bar layout.
Fig. 23 Power module layout with paralleling half-bridge configurations. (a) Package layout. (b) Bus bar layout.CC-BY · From the PDF
Fig. 24 Modeling of the layout with paralleling half-bridges.
Fig. 24 Modeling of the layout with paralleling half-bridges.CC-BY · From the PDF
Fig. 25 Simulation result of current sharing performance with paralleling half-bridge configurations. (a) Current waveform of the top devices. (b) Current waveform of the bottom devices.
Fig. 25 Simulation result of current sharing performance with paralleling half-bridge configurations. (a) Current waveform of the top devices. (b) Current waveform of the bottom devices.CC-BY · From the PDF
Fig. 26 Power module layout with auxiliary connection and its modeling. (a) Package layout. (b) Equivalent circuit.
Fig. 26 Power module layout with auxiliary connection and its modeling. (a) Package layout. (b) Equivalent circuit.CC-BY · From the PDF
Fig. 27 Experimental Current waveforms in a multichip power module. (a) Without auxiliary source connection. (b) With auxiliary source connection.
Fig. 27 Experimental Current waveforms in a multichip power module. (a) Without auxiliary source connection. (b) With auxiliary source connection.CC-BY · From the PDF
Fig. 28 Improved power module design for dynamic current imbalance mitigation.
Fig. 28 Improved power module design for dynamic current imbalance mitigation.CC-BY · From the PDF
Fig. 29 Experimental dynamic current imbalance mitigation results.
Fig. 29 Experimental dynamic current imbalance mitigation results.CC-BY · From the PDF
Fig. 30 Substrate layout design with different wire-bonding lengths.
Fig. 30 Substrate layout design with different wire-bonding lengths.CC-BY · From the PDF
Image 31
CC-BY · From the PDF
Fig. 32 Circuit topology of the adjustable V gs gate driver [99].
Fig. 32 Circuit topology of the adjustable V gs gate driver [99].CC-BY · From the PDF
Fig. 33 Experimental results of the parallel-connected device with variable gate voltage AGD. (a) Without AGD. (b) With AGD.
Fig. 33 Experimental results of the parallel-connected device with variable gate voltage AGD. (a) Without AGD. (b) With AGD.CC-BY · From the PDF
Fig. 34 Summary of the state-of-the-art current sharing methodologies.
Fig. 34 Summary of the state-of-the-art current sharing methodologies.CC-BY · From the PDF
Image 35
CC-BY · From the PDF
Image 36
CC-BY · From the PDF
Image 37
CC-BY · From the PDF
Image 38
CC-BY · From the PDF
Image 39
CC-BY · From the PDF

Verification

Claims the paper makes

65 Own interpretation · 59 Sources not found · 14 No basis given · 13 Own result

54 more claims

Create a free account to see all 151 claims and every source verdict.

See all claims — free account
  • It may state two separate claims as one. 78
  • Probably not a substantial claim. 22

Create a free account to see these claims.

Create a free account to see these assumptions.

Self-check

Percentages, sums and reported differences re-computed from the paper’s own numbers.

Each contradiction between two passages listed here was confirmed by an independent check.

2 of 2

Citations

Cites

Show all 121 references

Research works printed but not linked: 5

  1. regardi, 2020, How Infineon Controls and Assures the Reliability of SiC Based Power Semiconductors
  2. lin, 2018, Power SiC 2018 Materials Devices and Applications
  3. friedrichs, 2020, High Performance Coolsic MOSFET Technology With Silicon Like Reliability
  4. balogh, 2018, Fundamentals of MOSFET and IGBT Gate Driver Circuits
  5. hofmann, 2018, Evaluation of Potentials for Infineon Sic-Mosfets in Automotive Inverter Applications

Cited by

Related

See all

Metadata

Authors
Li, H., Zhao, S., Wang, X., Ding, L., & Mantooth, H. A.
Affiliations
  • Hefei University of Technology (CN)
  • KTH Royal Institute of Technology (SE)
  • University of Arkansas at Fayetteville (US)
ORCID
Venue
IEEE Transactions on Power Electronics
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Published
2023-08
Volume
38
Issue
8
Pages
9731-9749
ISSN
  • 0885-8993 (ISSN-L)
  • 1941-0107
DOI
10.1109/tpel.2023.3278270
OpenAlex
W4377291033
Cited by
135
References
121
Citations by year
2026: 35 · 2025: 65 · 2024: 28 · 2023: 7
FWCI
9.51
Type
journal article
Language
en
Open access
Licence
Locations
  • IEEE Transactions on Power Electronics (publishedVersion, cc-by)
  • VBN Forskningsportal (Aalborg Universitet) (publishedVersion, cc-by)
Funders
  • Anhui Natural Science Foundation (2208085QE164)
  • Higher Education Discipline Innovation Project (BP0719039)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Silicon Carbide Semiconductor Technologies
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced DC-DC Converters
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Multilevel Inverters and Converters
Keywords
SiC MOSFET, parallel connection, current imbalance, current sharing, parasitic parameters, power semiconductor reliability, high-speed switching

About these checks

Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.

A language model drew the claims from the paper on 2026-11-12, under version 3 of the claim definition (model deepseek-v4.1-flash, prompt extract-v3).

A second model labelled each claim on 2026-11-12 (model jev-1.13-20260917, definition revision gold-guideline-v0.2).

Statistics and arithmetic are recomputed, not judged.

Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.

What counts as a claim ›How we measure confidence ›How we check this ›

Are you an author, or do you see a problem with this page? Request a review

Data sources

Bibliographic data: Semantic Scholar, OpenAlex, Crossref.

Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).

Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.