AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers
Open accessAbstract
Low-precision arithmetic operations to accelerate deep-learning applications on field-programmable gate arrays (FPGAs) have been studied extensively, because they offer the potential to save silicon area or increase throughput. However, these benefits come at the cost of a decrease in accuracy. In this article, we demonstrate that reconfigurable constant coefficient multipliers (RCCMs) offer a better alternative for saving the silicon area than utilizing low-precision arithmetic. RCCMs multiply input values by a restricted choice of coefficients using only adders, subtractors, bit shifts, and multiplexers (MUXes), meaning that they can be heavily optimized for FPGAs. We propose a family of RCCMs tailored to FPGA logic elements to ensure their efficient utilization. To minimize information loss from quantization, we then develop novel training techniques that map the possible coefficient representations of the RCCMs to neural network weight parameter distributions. This enables the usage of the RCCMs in hardware, while maintaining high accuracy. We demonstrate the benefits of these techniques using AlexNet, ResNet-18, and ResNet-50 networks. The resulting implementations achieve up to 50% resource savings over traditional 8-bit quantized networks, translating to significant speedups and power savings. Our RCCM with the lowest resource requirements exceeds 6-bit fixed point accuracy, while all other implementations with RCCMs achieve at least similar accuracy to an 8-bit uniformly quantized design, while achieving significant resource savings.
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The AddNet approach gives better accuracy than a network that constrains weight parameters to binary values.
“This approach gives better accuracy than the network that constrain weight parameters to have binary value.”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [34]
The Accuracy Versus Area section (p. 12) reports that AddNet improves accuracy over 4-bit and 6-bit fixed-point implementations. It does not report an accuracy comparison with a network whose weights are constrained to binary values, so the specific comparator in the claim is unsupported. (LLM, conf=0.82)
Experimental — accuracy not yet measuredImplementing RCCM and AddNet saved resources by up to 50% more than a standard 8-bit quantized network with similar accuracy.
“The result of implementing RCCM and AddNet was the ability to save resources by up to 50% more than a standard 8-bit quantized network with similar accuracy [34].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [34]
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Ullah, S., & Kumar, A. S. (2023) · Springer eBooks · doi:10.1007/978-3-031-21294-9_3
Visanthi., V. P. (2023) · International Journal Of Trendy Research In Engineering And Technology · doi:10.54473/ijtret.2023.7201
SYNTACTIC ANALYSIS OF ARITHMETIC EXPRESSIONS FOR OPTIMIZING THE OPERATION OF PROGRAMS
Peretiaha, M., Poltavets, M., Smelyakov, K., & Chupryna, A. (2023) · ГРААЛЬ НАУКИ · doi:10.36074/grail-of-science.14.04.2023.039
Dynamic Multi-bit Parallel Computing Method Based on Reconfigurable Structure
Jiang, L., Liu, S., Zhu, J., Shan, R., & Li, Y. (2024) · Lecture notes in computer science · doi:10.1007/978-981-97-0801-7_20
de Dinechin, F. D., & Kumm, M. (2023) · Springer eBooks · doi:10.1007/978-3-031-42808-1_24
Self-citationReconfigurable One-Adder Multiplication for CNN Acceleration
Kim, K., Lee, H., & Nguyen, X. T. (2024) · International Conference on Electronics, Information, and Communication (ICEIC) · doi:10.1109/iceic61013.2024.10457161
Implementation of Deep Neural Networks on FPGAs and Reconfigurable Edge Computing Devices
Tiwari, S., Sorrot, S., Mahato, B., & Gupta, S. K. S. (2024) · International Conference on Sustainability and Technological Advancements in Engineering Domain (SUSTAINED) · doi:10.1109/sustained63638.2024.11074200
Hybrid SORN Cross-Correlation Architecture for Low-Complexity FPGAs
Rust, J., Bärthel, M., Hülsmeier, N., & Steffen Paul, A. (2025) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2025.3600965
Kailani, O. A., Zhang, Y., & Zhao, W. (2025) · doi:10.1109/iccad66269.2025.11240881
Reconfigurable constant multipliers: hardware models, optimization algorithm and applications
Barbe, B., Ledoux, L., Volkova, A., & de Dinechin, F. D. (2026) · Microprocessors and Microsystems · doi:10.1016/j.micpro.2026.105270
FPGA-Based Handwritten Digit Recognition Using 3-D Hop Net and Equilibrium Optimization
Rao, A. T., Thamarai, M., & Krishna, B. T. (2026) · Canadian Journal of Electrical and Computer Engineering · doi:10.1109/icjece.2026.3665570
A novel design of high throughput power efficient multiply accumulate unit
Jayasanthi, M., Kalaivani, R., Sampoornam, K. P., & Nath, V. (2026) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-026-02629-8
A High-Efficiency, High-Accuracy Approximate Multiplier for DNN Accelerators
Vo, H.-L., & Nguyen, T. (2026) · International Conference on Communications and Electronics (ICCE) · doi:10.1109/icce70609.2026.11658496
- Authors
- Faraone, J., Kumm, M., Hardieck, M., Zipf, P., Liu, X., Boland, D., & Leong, P. H. W.
- Affiliations
- The University of Sydney (AU)
- Fulda University of Applied Sciences (DE)
- University of Kassel (DE)
- Venue
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Published
- 2020-01
- Volume
- 28
- Issue
- 1
- Pages
- 115-128
- ISSN
- 1063-8210 (ISSN-L)
- 1557-9999
- OpenAlex
- W2976047473
- Cited by
- 66
- References
- 42
- Citations by year
- 2026: 4 · 2025: 4 · 2024: 15 · 2023: 16 · 2022: 14 · 2021: 7 · 2020: 6
- FWCI
- 3.02
- Type
- journal article
- Language
- en
- Open access
- green
- arxiv.org
- Licence
- Locations
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- arXiv (Cornell University)
- Funders
- Australia–Germany Joint Research Co-operation Scheme
- German Academic Exchange Service (57388068)
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Computational Theory and Mathematics › Numerical Methods and Algorithms
- Keywords
- low-precision arithmetic, quantization, fixed-point arithmetic, FPGA resource utilization, AlexNet, ResNet-18, ResNet50, area and power efficiency
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