The DOI matches its Crossref record; 32 of the 32 references it cites were found in a registry or an index.
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process
Abstract
Complementary field-effect transistor (CFET) is a future transistor type with a high potential to be used beyond 3-nm technology nodes. Despite its high future value, studies related to CFETs mostly focused on the device aspects. In other words, the path of CFET full-chip IC design is not fully demystified, knowing that various design factors/steps (such as schematic, layout, parasitics, design flow) must be considered on top of device traits for full-chip level IC. Therefore, this study focuses on enlightening the remaining factors/steps for full-chip IC design. In detail, we notify the importance of parasitics from various aspects of CFET design and provide optimization solutions. Compared to nanosheet FET (NSFET) on the full-chip scale, CFET shows a reduction of the area by −48.2%, power by −29.4%, total wirelength by −32.5%, and the number of cells by −18.1%.
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According to the Imec device roadmap, GAAFET devices are expected to push technologies until 2032.
“According to the device roadmap of Imec 98 , the se devices are expected to push technologies until 2032.”
From Extreme ultraviolet lithography (2024) · cites this paper as [98]
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Flagged first, then by citations
Research works printed but not linked: 8
- 2018, International Roadmap for Device and Systems
- Bae, 3 nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications, 28.7.1
- Prasad, Buried power rails and back-side power grids: Arm CPU power delivery network design beyond 5 nm, 19.1.1
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Cited by
Sorted by citations
Extreme ultraviolet lithography
Kazazis, D., Santaclara, J. G., van Schoot, J., Mochi, I., & Ekinci, Y. (2024) · Nature Reviews Methods Primers · doi:10.1038/s43586-024-00361-z · Cited by 149
Metadata
- Authors
- Park, E., & Song, T.
- Affiliations
- Pohang University of Science and Technology (KR)
- Kyungpook National University (KR)
- Venue
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Published
- 2023-02
- Volume
- 31
- Issue
- 2
- Pages
- 177-187
- ISSN
- 1063-8210 (ISSN-L)
- 1557-9999
- OpenAlex
- W4312992159
- Cited by
- 47
- References
- 32
- Citations by year
- 2026: 11 · 2025: 23 · 2024: 6 · 2023: 7
- FWCI
- 2.47
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems (publishedVersion)
- Funders
- National Research and Development Program through the National Research Foundation of Korea
- Ministry of Science and ICT (2020M3H2A1078045)
- Basic Science Research Program through the National Research Foundation of Korea
- Ministry of Education (2022R1I1A3073214)
- IC Design Education Center (IDEC), Korea
- Samsung Electronics Company, Ltd
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
- Keywords
- CFET, parasitic effects, 3 nm technology node, nanosheet FET, energy consumption reduction, wirelength minimization, area reduction, design flow
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