The DOI matches its Crossref record; 20 of the 20 references it cites were found in a registry or an index.
Dark silicon and the end of multicore scaling
Abstract
Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to which the shift to multicore parts is partially a response, may soon limit multicore scaling just as single-core scaling has been curtailed. This paper models multicore scaling limits by combining device scaling, single-core scaling, and multicore scaling to measure the speedup potential for a set of parallel workloads for the next five technology generations. For device scaling, we use both the ITRS projections and a set of more conservative device scaling parameters. To model singlecore scaling, we combine measurements from over 150 processors to derive Pareto-optimal frontiers for area/performance and power/performance. Finally, to model multicore scaling, we build a detailed performance model of upper-bound performance and lowerbound core power. The multicore designs we study include singlethreaded CPU-like and massively threaded GPU-like multicore chip organizations with symmetric, asymmetric, dynamic, and composed topologies. The study shows that regardless of chip organization and topology, multicore scaling is power limited to a degree not widely appreciated by the computing community. Even at 22 nm (just one year from now), 21 % of a fixed-size chip must be powered off, and at 8 nm, this number grows to more than 50%. Through 2024, only 7.9 × average speedup is possible across commonly used parallel workloads, leaving a nearly 24-fold gap from a target of doubled performance per generation.
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Cites
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Cited by
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network
Sharma, H., Park, J., Suda, N., Lai, L., Chau, B., Kim, J. K., Chandra, V., & Esmaeilzadeh, H. (2018) · 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca.2018.00069 · Cited by 543
Self-citationHeracles: improving resource efficiency at scale
Lo, D., Cheng, L., Govindaraju, R., Ranganathan, P., & Kozyrakis, C. (2015) · Proceedings of the 42nd Annual International Symposium on Computer Architecture · doi:10.1145/2749469.2749475 · Cited by 466
Trimberger, S. M. S. (2018) · IEEE Solid-State Circuits Magazine · doi:10.1109/mssc.2018.2822862 · Cited by 77
A Cost and Power Feasibility Analysis of Quantum Annealing for NextG Cellular Wireless Networks
Kasi, S., Warburton, P., Kaewell, J., & Jamieson, K. (2023) · IEEE Transactions on Quantum Engineering · doi:10.1109/tqe.2023.3326469 · Cited by 20
Metadata
- Authors
- Esmaeilzadeh, H., Blem, E., St. Amant, R., Sankaralingam, K., & Burger, D.
- Venue
- Proceedings of the 38th annual international symposium on Computer architecture
- Publisher
- ACM
- Published
- 2011-06-04
- Pages
- 365-376
- ISSN
- 1063-6897 (ISSN-L)
- OpenAlex
- W2006312753
- Cited by
- 1,532
- References
- 20
- FWCI
- 87.22
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Esmaeilzadeh, H., Blem, E., St. Amant, R., Sankaralingam, K., & Burger, D. (2011). Dark silicon and the end of multicore scaling. Proceedings of the 38th annual international symposium on Computer architecture. https://doi.org/10.1145/2000064.2000108
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