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The Next Generation of Deep Learning Hardware: Analog Computing

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RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars

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Signal and noise extraction from analog memory elements for neuromorphic computing

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Algorithm for Training Neural Networks on Resistive Device Arrays

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Inference of Long-Short Term Memory networks at software-equivalent accuracy using 2.5M analog Phase Change Memory devices

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The marriage of training and inference for scaled deep learning analog hardware

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Neural network accelerator design with resistive crossbars: Opportunities and challenges

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Deep physical neural networks trained with backpropagation

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Hardware implementation of memristor-based artificial neural networks

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A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

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Research Progress on Memristor: From Synapses to Computing Systems

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Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators

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Memristor-based hardware accelerators for artificial intelligence

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MemTorch: An Open-source Simulation Framework for Memristive Deep Learning Systems

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A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh

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A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security

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Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inference

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Optimised weight programming for analogue memory-based deep neural networks

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Side-Channel Attack Analysis on In-Memory Computing Architectures

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Fast and robust analog in-memory deep neural network training

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Neural architecture search for in-memory computing-based deep learning accelerators

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Gradient-Based Neuromorphic Learning on Dynamical RRAM Arrays

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The role of analog signal processing in upcoming telecommunication systems: Concept, challenges, and outlook

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Rapid learning with phase-change memory-based in-memory computing through learning-to-learn

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CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool

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Material to system-level benchmarking of CMOS-integrated RRAM with ultra-fast switching for low power on-chip learning

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Impact of Asymmetric Weight Update on Neural Network Training With Tiki-Taka Algorithm

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Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices

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Modeling and simulating in-memory memristive deep learning systems: An overview of current efforts

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Metal-organic framework single crystal for in-memory neuromorphic computing with a light control

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Framework for In-Memory Computing Based on Memristor and Memcapacitor for On-Chip Training

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All‐in‐One Analog AI Hardware: On‐Chip Training and Inference with Conductive‐Metal‐Oxide/HfOx ReRAM Devices

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Doping modulated ion hopping in tantalum oxide based resistive switching memory for linear and stable switching dynamics

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PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators

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ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits

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AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computing

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Retention-aware zero-shifting technique for Tiki-Taka algorithm-based analog deep learning accelerator

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A Simulation Framework for Memristor-Based Heterogeneous Computing Architectures

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Progress and challenges of phase change memory for in-memory computing

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X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation

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AnalogVNN: A fully modular framework for modeling and optimizing photonic neural networks

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When in-memory computing meets spiking neural networks—A perspective on device-circuit-system-and-algorithm co-design

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Proton‐Modulated Resistive Switching in a Synapse‐Like Tyrosine‐Rich Peptide‐Based Memristor

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Advancements in Artificial Intelligence Circuits and Systems (AICAS)

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A System for Validating Resistive Neural Network Prototypes

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BNN An Ideal Architecture for Acceleration With Resistive in Memory Computation

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Examining the Role and Limits of Batchnorm Optimization to Mitigate Diverse Hardware-noise in In-memory Computing

Bhattacharjee, A., Moitra, A., Kim, Y., Venkatesha, Y., & Panda, P. (2023) · ACM Great Lakes Symposium on VLSI (GLSVLSI) · doi:10.1145/3583781.3590241 · Cited by 11

Solving sparse linear systems with approximate inverse preconditioners on analog devices

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Surface roughness engineering for improvement of cycle-to-cycle variability of RRAM

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Improving the Accuracy of Analog-Based In-Memory Computing Accelerators Post-Training

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FADESIM: Enable Fast and Accurate Design Exploration for Memristive Accelerators Considering Nonidealities

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Xpikeformer: Hybrid Analog-Digital Hardware Acceleration for Spiking Transformers

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Error-aware probabilistic training for memristive neural networks

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Top Python-Based Deep Learning Packages: A Comprehensive Review

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WOx channel engineering of Cu-ion-driven synaptic transistor array for low-power neuromorphic computing

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The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming

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Field Induced Off‐State Instability in InGaZnO Thin‐Film Transistor and its Impact on Synaptic Circuits

Kang, M., Cho, U., Kang, J., Han, N., Seo, H. J., Yang, J., Shin, S., Kim, T., Kim, S., Jeong, C., et al. (2024) · Advanced Electronic Materials · doi:10.1002/aelm.202300900 · Cited by 7

Sino-Iranian Cooperation in Artificial Intelligence: A Potential Countering Against the US Hegemony

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Design Space Exploration of Dense and Sparse Mapping Schemes for RRAM Architectures

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Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited)

Frank, M. M., Li, N., Rasch, M. J., Jain, S., Chen, C.-T., Muralidhar, R., Han, J., Narayanan, V., Philip, T. M., Brew, K. W., et al. (2023) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps48203.2023.10117874 · Cited by 9

Strategy to improve synaptic behavior of ion-actuated synaptic transistors—the use of ion blocking layer to improve state retention

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Demonstration of transformer-based ALBERT model on a 14nm analog AI inference chip

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In situ spectral reconstruction based on a memristor chip for energy-efficient computational spectrometry

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Solving Sparse Linear Systems via Flexible GMRES with In-Memory Analog Preconditioning

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Demonstration of transfer learning using 14 nm technology analog ReRAM array

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Linear Synaptic Weight Update in Selector-Less HfO₂ RRAM Using Al₂O₃ Built-In Resistor for Neuromorphic Computing Systems

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Linear Conductance Modulation in Aluminum Doped Resistive Switching Memories for Neuromorphic Computing

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Accelerating AI using next-generation hardware: Possibilities and challenges with analog in-memory computing

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Spiking CMOS-NVM mixed-signal neuromorphic ConvNet with circuit- and training-optimized temporal subsampling

Dorzhigulov, A., & Saxena, V. (2023) · Frontiers in Neuroscience · doi:10.3389/fnins.2023.1177592 · Cited by 6

Interfacing Neuromorphic Hardware with Machine Learning Frameworks - A Review

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Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware

Staudigl, F., Fetz, T., Pelke, R., Šišejković, D., Joseph, J. M., Pöhls, L. B., & Leupers, R. (2023) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1109/dac56929.2023.10247742 · Cited by 7

Internal Resistor Effect of Multilayer-Structured Synaptic Device for Low-Power Operation

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Low-power, linear, and uniform bimodal resistive switching in proton conducting/insulating bilayer-based memristor

Yoon, J. H., Song, M., Song, Y., Park, J.-M., & Kwon, J. (2024) · Journal of Alloys and Compounds · doi:10.1016/j.jallcom.2024.174251 · Cited by 5

Toolflow for the algorithm-hardware co-design of memristive ANN accelerators

Wabnitz, M., & Gemmeke, T. (2023) · Memories - Materials Devices Circuits and Systems · doi:10.1016/j.memori.2023.100066 · Cited by 5

Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations

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Integration of Physics-Derived Memristor Models with Machine Learning Frameworks

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Organic–Inorganic Hybrid Synaptic Transistors: Methyl-Silsesquioxanes-Based Electric Double Layer for Enhanced Synaptic Functionality and CMOS Compatibility

Hwang, T.-G., Park, H., & Cho, W.-J. (2024) · Biomimetics · doi:10.3390/biomimetics9030157 · Cited by 4

Difficulties and approaches in enabling learning-in-memory using crossbar arrays of memristors

Wang, W. J., Li, Y., & Wang, M. (2024) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/ad6732 · Cited by 4

Parameter Space Exploration of Neural Network Inference Using Ferroelectric Tunnel Junctions for Processing-In-Memory

Hosseinzadeh, S., Lancaster, S., Parvaresh, A., Silva, C., Mikolajick, T., Slesazeck, S., & Fey, D. (2024) · Euromicro Conference on Digital System Design (DSD) · doi:10.1109/dsd64264.2024.00010 · Cited by 4

NORA: Noise-Optimized Rescaling of LLMs on Analog Compute-in-Memory Accelerators

Hou, Y. T., Tsai, H.-Y. S., Maghraoui, K. E., Gokmen, T., Burr, G. W., & Liu, L. (2025) · Design, Automation, and Test in Europe · doi:10.23919/date64628.2025.10993217 · Cited by 4

Kernel approximation using analogue in-memory computing

Büchel, J., Camposampiero, G., Vasilopoulos, A., Lammie, C., Gallo, M. L., Rahimi, A., & Sebastian, A. (2024) · Nature Machine Intelligence · doi:10.1038/s42256-024-00943-2 · Cited by 4

Noise-Agnostic One-Shot Training and Retraining for Robust DNN Inferencing on Analog Compute-in-Memory Systems

Bommana, A. R., Feinberg, B., Xiao, P., Bennet, C., Marinella, M. J., & Chakrabarty, K. (2026) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1109/asp-dac66049.2026.11420230 · Cited by 3

Analog Switching in Hexagonal Boron Nitride Memristors via Multiple Nano‐Filaments Confinement

Song, J., Moon, S., Byun, J., Kim, J., Choi, J., Kwak, H., Hwang, I., Ji, C., Kim, S., & Kim, J. K. (2025) · Small · doi:10.1002/smll.202504507 · Cited by 3

Pedestrian Trajectory Prediction Based on SOPD-GAN Used for the Trajectory Planning and Motion Control of Mobile Robot

Li, H., Qian, D., Liu, G., Cui, Z. Q., & Lei, J. (2023) · IEEE Access · doi:10.1109/access.2023.3330376 · Cited by 3

Synaptogen: A Cross-Domain Generative Device Model for Large-Scale Neuromorphic Circuit Design

Hennen, T., Brackmann, L., Ziegler, T., Siegel, S., Menzel, S., Waser, R. M., Wouters, D. J., & Bedau, D. (2024) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2024.3427616 · Cited by 3

Memory Technologies for Crossbar Array Design: A Comparative Evaluation of Their Impact on DNN Accuracy

Victor, J., Wang, C., & Gupta, S. K. (2025) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2025.3550314 · Cited by 3

A Software-Circuit-Device Co-Optimization Framework for Neuromorphic Inference Circuits

Quibuyen, P., Jiao, T., & Wong, H. Y. (2022) · IEEE Access · doi:10.1109/access.2022.3167709 · Cited by 4

Prospects of analog in-memory computing using ferroelectric tunnel junctions

Borg, M., Papadopoulos, C., Guerin, A., Athle, R., & Bastani, S. (2025) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/add0d9 · Cited by 3

V-PCMixer: incorporating 3D vertical phase-change memory based analog in-memory computing in mixer architecture

Choi, S., & Kim, S. (2025) · Nanoscale · doi:10.1039/d5nr00814j · Cited by 2

A Framework for Automatic Synthesis of Neuromorphic Architectures with Heterogeneous Integration of CMOS and Memristors

Johari, S., Mohammadhassani, A., & Das, A. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11043873 · Cited by 2

Energy-convergence trade off for the training of neural networks on bio-inspired hardware

Garg, N., Vicandi, P. U., Zhang, Y., Baigol, A., Falcone, D. F., Ram, M. S., Offrein, B. J., & Bégon‐Lours, L. (2025) · doi:10.1109/ccmcc67628.2025.11380809 · Cited by 2

LIMCA: LLM for Automating Analog In-Memory Computing Architecture Design Exploration

Vungarala, D., Amin, M. H., Mercati, P., Ghosh, A., Roohi, A., Pan, D. Z., Zand, R., & Angizi, S. (2026) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2026.3694341 · Cited by 2

Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited)

Burr, G. W., Narayanan, P., Ambrogio, S., Okazaki, A., Tsai, H.-Y. S., Hosokawa, K., Mackin, C., Nomura, A., Yasuda, T., Demarest, J. J., et al. (2023) · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · doi:10.23919/vlsitechnologyandcir57934.2023.10185411 · Cited by 2

Enhanced temporal variation of resistive switching memories by insertion of rough titanium oxide thin film

Song, Y., Yoon, J. H., Lee, S., Ham, W., Park, J.-M., Lee, J., & Kwon, J. (2023) · Applied Physics Letters · doi:10.1063/5.0158280 · Cited by 2

Practical hardware demonstration of a multi-sensor goal-oriented semantic signal processing and communications network

Akkoç, S., Çınar, A., Ercan, B., Kalfa, M., & Arıkan, O. (2024) · Journal of the Franklin Institute · doi:10.1016/j.jfranklin.2024.107363 · Cited by 2

MemMIMO: A Simulation Framework for Memristor-Based Massive MIMO Acceleration

Xu, J., Zheng, Y., Stathis, D., Wang, R., Shen, R., Zheng, L., Zou, Z., & Hemani, A. (2025) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2025.3565478 · Cited by 2

Attention-driven PCM-based In-Memory Computing for Smart Vision Systems

Haidar, A., Khan, A., Ntinas, V. G., Fernández‐Berni, J., Carmona‐Galán, R., & Tetzlaff, R. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11044041 · Cited by 2

A Realistic Simulation Framework for Analog/Digital Neuromorphic Architectures

Quintana, F. M., Maryada, M., Galindo, P. L., Donati, E., Indiveri, G., & Perez‐Peña, F. (2025) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/adef77 · Cited by 2

Efficient transformer adaptation for analog in-memory computing via low-rank adapters

Li, C., Ferro, E., Lammie, C., Gallo, M. L., Boybat, I., & Rajendran, B. (2026) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/ae405e · Cited by 4

A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations

Kao, H.-Y., & Huang, S.-H. (2022) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas54282.2022.9869956 · Cited by 2

Configuration through Optimization for In-Memory Computing Hardware and Simulators

Li, K., Hsu, C.-F., Lin, Y.-S., Chien, S., & Chen, W. (2022) · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · doi:10.1109/sips55645.2022.9919208 · Cited by 2

A Parallel SystemC Virtual Platform for Neuromorphic Architectures

Galicia, M., Merchant, F., & Leupers, R. (2022) · International Symposium on Quality Electronic Design (ISQED) · doi:10.1109/isqed54688.2022.9806235 · Cited by 2

Design Framework for ReRAM-Based DNN Accelerators with Accuracy and Hardware Evaluation

Kao, H.-Y., Huang, S.-H., & Cheng, W. (2022) · Electronics · doi:10.3390/electronics11132107 · Cited by 2

PyMem: A Graphical User Interface Tool for Neuromemristive Hardware–Software Co-Design

Radhakrishnan, A., Palliyalil, J., Babu, S., Dorzhigulov, A., & James, A. P. (2024) · IEEE Open Journal of the Industrial Electronics Society · doi:10.1109/ojies.2024.3363093 · Cited by 3

Enabling Selective and Tunable Weight Updates in All-InGaZnO 3-Transistor 1-Capacitor Synaptic Circuits for On-Chip Training

Kang, M., Kim, M., Kang, J., Won, J., Seo, H. J., Joe, C., Roh, Y., Park, Y., & Kim, S. (2025) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2025.3576795 · Cited by 1

Weight nonlinear mapping based memristor crossbar array implementation scheme for convolutional neural network off-chip training

Lin, Z., Chen, Z., Zhang, J., Deng, J., Wu, X., & Feng, Y. (2025) · Expert Systems with Applications · doi:10.1016/j.eswa.2025.129277 · Cited by 1

Comparative Analysis of Inference Performance of Pre-Trained Convolutional Neural Networks in Analog Accelerators

Rahman, M., & Qian, L. (2025) · IEEE Transactions on Emerging Topics in Computational Intelligence · doi:10.1109/tetci.2025.3641703 · Cited by 1

Designing and Modeling Analog Neural Network Training Accelerators

Agarwal, S., Jacobs-Gedrim, R. B., Bennett, C. H., Hsia, A., Heukelom, M. S. V., Hughart, D. R., Fuller, E. J., Li, Y., Talin, A. A., & Marinella, M. J. (2019) · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · doi:10.1109/vlsi-tsa.2019.8804680 · Cited by 8

Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited)

Hosokawa, K., Narayanan, P., Ambrogio, S., Tsai, H.-Y. S., Mackin, C., Fasoli, A., Friz, A. M., Chen, A., Luquin, J., Spoon, K., et al. (2021) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas51556.2021.9401128 · Cited by 1

Middleware and toolkit for next generation analog AI hardware acceleration

Maghraoui, K. E., & Carta, F. (2021) · doi:10.1145/3491085.3502278

Hardware-Aware Model Design and Training of Silicon-based Analog Neural NetworksPreprint

Filippeschi, G., Brazzini, M., Mosquera, C., Lanuzza, M., Catania, A., Strangio, S., & Iannaccone, G. (2025) · arXiv (Cornell University)

On the Viability of End-to-End Neural Networks in the Analog Domain

Ige, A., Ayyappan, P. R., & Hasler, J. (2026) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2026.3703087