Non-monotonic threshold voltage variation in 4H-SiC metal–oxide–semiconductor field-effect transistor: Investigation and modeling

Abstract

We propose an analytical model to reproduce the non-monotonic instability of the threshold voltage in 4H-SiC MOSFETs submitted to a positive gate stress bias. Experimental analysis of the threshold voltage transients indicates that both electron and hole trappings take place in the gate dielectric or at the dielectric/semiconductor interface, responsible for a VTH increasing–decreasing–increasing pattern. At low/moderate stress fields (<7 MV/cm), the electron trapping kinetics responsible for a positive VTH shift are modeled by a rate equation considering a trapping-inhibition model, which explains the logarithmic degradation kinetics. In the high field regime (>8 MV/cm), we propose that electrons can tunnel through the SiO2, be accelerated by the high field, and generate holes through impact ionization (II) or anode hole injection. These holes are then trapped in the oxide, thus generating a negative VTH shift. This second process has an exponential time-dependency, as found through the analysis of the corresponding rate equations. The time constant of the positive VTH shift is evaluated as a function of stress voltage and temperature. The results indicate that the time constant is strongly dependent on the electric field (that accelerates electrons to generate holes), and not thermally activated, in agreement with theoretical considerations.