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Four-dimensional address topology for circuits with stacked multilayer crossbar arrays
Open accessAbstract
We present a topological framework that provides a simple yet powerful electronic circuit architecture for constructing and using multilayer crossbar arrays, allowing a significantly increased integration density of memristive crosspoint devices beyond the scaling limits of lateral feature sizes. The truly remarkable feature of such circuits, which is an extension of the CMOL (Cmos + MOLecular-scale devices) concept for an area-like interface to a three-dimensional system, is that a large-feature-size complimentary metal-oxide-semiconductor (CMOS) substrate can provide high-density interconnects to multiple crossbar layers through a single set of vertical vias. The physical locations of the memristive devices are mapped to a four-dimensional logical address space such that unique access from the CMOS substrate is provided to every device in a stacked array of crossbars. This hybrid architecture is compatible with digital memories, field-programmable gate arrays, and biologically inspired adaptive networks and with state-of-the-art integrated circuit foundries.
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“Generally, Eq. (4) can be seen as a modification of the Duffing oscillator equation, whose chaotic properties are well-known 16 .”
From Bistable Nonvolatile Elastic-Membrane Memcapacitor Exhibiting a Chaotic Behavior (2011) · cites this paper as [16]
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Cites
Strukov, D. B., Snider, G. S., Stewart, D. R., & Williams, R. S. (2008) · Nature · doi:10.1038/nature06932 · Cited by 11,828
Self-citationMemristor—The Missing Circuit Element
Chua, L. (1971) · IEEE Transactions on Circuit Theory · doi:10.1109/tct.1971.1083337 · Cited by 10,268 · cited 1×
“Amemristorisa two-terminalelectricalcircuitelementthatchangesitsresistance dependingonthetotalamountofchargethatflowsthroughthe device(6,7).”
Nanoionics-based resistive switching memories
Waser, R., & Aono, M. (2007) · Nature Materials · doi:10.1038/nmat2023 · Cited by 4,923
Analog VLSI and Neural Systems
Mead, C. (1989) · CaltechAUTHORS (California Institute of Technology) · Cited by 2,776
Memristive devices and systems
Chua, L. O., & Kang, S. M. (1976) · Proceedings of the IEEE · doi:10.1109/proc.1976.10092 · Cited by 2,604 · cited 1×
“A memristor is a two-terminal electrical circuit element that changes its resistance depending on the total amount of charge that flows through the device (6, 7).”
BackgroundDevice scaling limits of Si MOSFETs and their application dependencies
Frank, D. J., Dennard, R. H., Nowak, E., Solomon, P. M., Taur, Y., & Wong, H. ‐. P. (2001) · Proceedings of the IEEE · doi:10.1109/5.915374 · Cited by 1,576
A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre
Green, J. E., Choi, J. W., Boukai, A. I., Bunimovich, Y. L., Johnston‐Halperin, E., DeIonno, E., Luo, Y., Sheriff, B. A., Xu, K., Shin, Y. S., et al. (2007) · Nature · doi:10.1038/nature05462 · Cited by 1,230
Electrical phenomena in amorphous oxide films
Dearnaley, G., Stoneham, A. M., & Morgan, D. V. (1970) · Reports on Progress in Physics · doi:10.1088/0034-4885/33/3/306 · Cited by 731
Memristor−CMOS Hybrid Integrated Circuits for Reconfigurable Logic
Xia, Q., Robinett, W., Cumbie, M. W., Banerjee, N., Cardinali, T. J., Yang, J. J., Wu, W., Li, X., Tong, W. M., Strukov, D. B., et al. (2009) · Nano Letters · doi:10.1021/nl901874j · Cited by 671
Self-citationNanoscale molecular-switch crossbar circuits
Chen, Y., Jung, G. Y., Ohlberg, D. A. A., Li, X., Stewart, D. R., Jeppesen, J. O., Nielsen, K. A., Stoddart, J. F., & Williams, R. S. (2003) · Nanotechnology · doi:10.1088/0957-4484/14/4/311 · Cited by 633
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Asymptotic enumeration of binary matrices with bounded row and column weights
Ordentlich, E., Parvaresh, F., & Roth, R. M. (2011) · IEEE International Symposium on Information Theory (ISIT) · doi:10.1109/isit.2011.6033804 · Cited by 6
KARAKULAK, E., MUTLU, R., & Uçar, E. (2014) · Trakya University's Institutional Open Access System (Trakya University) · Cited by 6
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Mapping of image and network processing tasks on high-throughput CMOL FPGA circuits
Madhavan, A., & Strukov, D. B. (2012) · IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC) · doi:10.1109/vlsi-soc.2012.6379010 · Cited by 6
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Stuart, M., & Manic, M. (2017) · Annual Conference of the IEEE Industrial Electronics Society (IECON) · doi:10.1109/iecon.2017.8217271 · Cited by 6
Chua, L. O. (2013) · Springer eBooks · doi:10.1007/978-3-319-02630-5_1 · Cited by 6
3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers
Chen, Y., Li, H. H., Chen, Y., & Pino, R. E. (2011) · Design, Automation, and Test in Europe · doi:10.1109/date.2011.5763289 · Cited by 6
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Merkel, C. E. (2011) · RIT Scholar Works (Rochester Institute of Technology) · Cited by 6
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Mohsin, F. (2010) · International Conference on Computer and Information Technology (ICCIT) · doi:10.1109/iccitechn.2010.5723881 · Cited by 5
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Morgul, M. C., Peker, F., & Altun, M. (2016) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi.2016.100 · Cited by 5
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Aljafar, M. J., Long, P., & Perkowski, M. A. (2016) · BioNanoScience · doi:10.1007/s12668-016-0213-1 · Cited by 5
Memristor–CMOS hybrid ultra-low-power high-speed multivibrators
Vidhyadharan, A. S., & Vidhyadharan, S. (2021) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-021-01856-5 · Cited by 5
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Vourkas, I., & Sirakoulis, G. C. (2013) · Springer eBooks · doi:10.1007/978-3-319-02630-5_23 · Cited by 5
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Mane, P. S., Talati, N., Riswadkar, A., Jasani, B. A., & Ramesha, C. K. (2015) · International Conference on VLSI Design · doi:10.1109/vlsid.2015.94 · Cited by 5
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Cerofolini, G. F. (2011) · Applied Physics A · doi:10.1007/s00339-011-6724-2 · Cited by 4
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Pickett, M. D. (2010) · eScholarship (California Digital Library) · Cited by 4
Modeling Memristor–Based Circuit Networks on Crossbar Architectures
Vourkas, I., & Sirakoulis, G. C. (2019) · Springer eBooks · doi:10.1007/978-3-319-76375-0_34 · Cited by 3
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Poikonen, J. H., Lehtonen, E., Laiho, M., & Poikonen, J. K. (2014) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2014.2361071 · Cited by 3
Memristor Device Engineering and CMOS Integration for Reconfigurable Logic Applications
Xia, Q. (2013) · Springer eBooks · doi:10.1007/978-1-4614-9068-5_11 · Cited by 3
Chua, L. O. (2019) · Springer eBooks · doi:10.1007/978-3-319-76375-0_1 · Cited by 2
Polymer-Based Memory Structures on Copper Substrates
Yahyaie, I., Khaper, T., Giesbrecht, P. K., & Freund, M. S. (2014) · Journal of The Electrochemical Society · doi:10.1149/2.100406jes · Cited by 2
Memristor-Based Resistive Computing
Kang, S.-M. S., & Shin, S. (2013) · Springer eBooks · doi:10.1007/978-1-4614-9068-5_10 · Cited by 2
High density crossbar structure for memory application
Kim, S. (2011) · Deep Blue (University of Michigan) · Cited by 2
Architecture for memristor-based storage structures
Lebeck, A. R., & Liu, Y. (2011) · Cited by 2
Combined Compute and Storage: Configurable Memristor Arrays to Accelerate SearchPreprint
Liu, Y., Dwyer, C., & Lebeck, A. R. (2016) · arXiv (Cornell University) · doi:10.48550/arxiv.1601.05273 · Cited by 2
Ferroelectric tunnel junctions
Garcia, V. (2020) · Kölner Universitäts PublikationsServer (Universität zu Köln) · doi:10.48550/arxiv.2011.07864 · Cited by 9
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Rouco, V., Lagarrigue, A., Humbert, V. F. C., de Dios, C., Carreira, S. J., Leon, C., Santamaria, J., & Villegas, J. E. (2025) · Applied Physics Letters · doi:10.1063/5.0304575 · Cited by 1
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Zhang, Y., Sipling, C., & Ventra, M. D. (2026) · New Journal of Physics · doi:10.1088/1367-2630/ae4137 · Cited by 1
Strukov, D. B., & Likharev, K. K. (2011) · IEEE International Conference on Nanotechnology (IEEE-NANO) · doi:10.1109/nano.2011.6144663 · Cited by 1
Self-citationMemristive Devices and Circuits
Erokhin, V. V. (2021) · Springer eBooks · doi:10.1007/978-3-030-79492-7_1 · Cited by 1
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Ordentlich, E., & Roth, R. M. (2013) · IEEE International Symposium on Information Theory (ISIT) · doi:10.1109/isit.2013.6620206 · Cited by 1
Li, Z., Li, Q., & Wen, D. (2017) · IEICE Transactions on Electronics · doi:10.1587/transele.e100.c.475 · Cited by 1
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Erokhin, V. V. (2021) · Springer eBooks · doi:10.1007/978-3-030-79492-7_7 · Cited by 1
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Lu, W. D., Jo, S., Yang, Y., Kvatinsky, S., Friedman, E. G., Avinoam Kolodny, A., Weiser, U. C., Kavehei, O., Skafidas, S., Eshraghian, K., et al. (2012) · Frontiers in Electronic Materials · doi:10.1002/9783527667703.ch40
Yoon, J. H., Jung, H., Lee, M. H., Kim, G. H., Song, S. J., Seok, J. Y., Yoon, K. J., Hwang, C. S., Besland, M., Tranchant, J., et al. (2012) · Frontiers in Electronic Materials · doi:10.1002/9783527667703.ch67
Self-citationFabric Mapping and Placement of Field Programmable Stateful Logic Array
Kim, K. (2012) · Journal of the Institute of Electronics and Information Engineers · doi:10.5573/ieek.2012.49.12.209
3D implication logic: Preliminary results
Adam, G. C. (2011) · International Conference on Field-Programmable Technology (FPT) · doi:10.1109/fpt.2011.6132687
On q-ary antipodal matchings and applications
Ordentlich, E., Roth, R. M., & Seroussi, G. (2012) · IEEE International Symposium on Information Theory (ISIT) · doi:10.1109/isit.2012.6283027
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Alvbrant, J. (2016) · Linköping studies in science and technology. Thesis · doi:10.3384/lic.diva-126333
Electrical properties of metal-molecular nanoparticle networks: modeling and experiment
Zhang, P. (2016) · UVic’s Research and Learning Repository (University of Victoria)
Memory architectures for exaflop computing systems
Pavlović, M. (2016) · doi:10.5821/dissertation-2117-96269
Emerging run-time reconfigurable FPGA and CAD tools
Chen, Y. (2014) · D-Scholarship@Pitt (University of Pittsburgh)
Abhay, S. V., & Vidhyadharan, S. (2020) · Transactions on Electrical and Electronic Materials · doi:10.1007/s42341-020-00253-5
Reliable High Density Stacked Memristor Memory Designs
Vadivelmurugan, S. (2018) · doi:10.14569/specialissue.2018.0901123
Li, H., & Chen, Y. (2011) · CRC Press eBooks · doi:10.1201/b11354-5
Halide Perovskites for Neuromorphic Computing
Vasilopoulou, M., Davazoglou, K., Yusoff, A. R. B. M., Chai, Y., Noh, Y., Anthopoulos, T. D., & Nazeeruddin, M. K. (2023) · Royal Society of Chemistry eBooks · doi:10.1039/bk9781839169946-00498
28 302Nano- und Molekularelektronik
Hartmann, U. (2025) · De Gruyter eBooks · doi:10.1515/9783486855449-006
Development of filamentary Memristive devices for synaptic plasticity implementation
Barbera, S. L. (2015) · theses.fr (ABES) · doi:10.70675/91a39e21z25c6z44d8zb0d3zd298023d1a34
Metadata
- Authors
- Strukov, D. B., & Williams, R. S.
- Affiliations
- Hewlett-Packard (United States) (US)
- Venue
- Proceedings of the National Academy of Sciences
- Publisher
- National Academy of Sciences
- Published
- 2009-12
- Volume
- 106
- Issue
- 48
- Pages
- 20155-20158
- ISSN
- 0027-8424 (ISSN-L)
- 1091-6490
- PMC
- PMC2777961
- OpenAlex
- W2031176269
- Cited by
- 153
- References
- 27
- Citations by year
- 2026: 1 · 2025: 2 · 2024: 2 · 2023: 4 · 2022: 5 · 2021: 10 · 2020: 7 · 2019: 6 · 2018: 9 · 2017: 8 · 2016: 8 · 2015: 10 · 2014: 9 · 2013: 18 · 2012: 17
- FWCI
- 14.02
- Type
- journal article
- Language
- en
- Open access
- green
- www.ncbi.nlm.nih.gov
- Locations
- Proceedings of the National Academy of Sciences (publishedVersion)
- PubMed Central (publishedVersion)
- PubMed (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › 3D IC and TSV technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
- Keywords
- CMOS substrate, vertical interconnects, integration density, neuromorphic hardware
- MeSH terms
- Computer Systems, Electronics, Semiconductors, Electric Impedance
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