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Four-dimensional address topology for circuits with stacked multilayer crossbar arrays
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We present a topological framework that provides a simple yet powerful electronic circuit architecture for constructing and using multilayer crossbar arrays, allowing a significantly increased integration density of memristive crosspoint devices beyond the scaling limits of lateral feature sizes. The truly remarkable feature of such circuits, which is an extension of the CMOL (Cmos + MOLecular-scale devices) concept for an area-like interface to a three-dimensional system, is that a large-feature-size complimentary metal-oxide-semiconductor (CMOS) substrate can provide high-density interconnects to multiple crossbar layers through a single set of vertical vias. The physical locations of the memristive devices are mapped to a four-dimensional logical address space such that unique access from the CMOS substrate is provided to every device in a stacked array of crossbars. This hybrid architecture is compatible with digital memories, field-programmable gate arrays, and biologically inspired adaptive networks and with state-of-the-art integrated circuit foundries.
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“Generally, Eq. (4) can be seen as a modification of the Duffing oscillator equation, whose chaotic properties are well-known 16 .”
From Bistable Nonvolatile Elastic-Membrane Memcapacitor Exhibiting a Chaotic Behavior (2011) · cites this paper as [16]
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Nanopatterns with a Square Symmetry from an Orthogonal Lamellar Assembly of Block Copolymers
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Variable conductivity of nanocomposite nickel oxide/porous silicon
Mares, J. W., Fain, J. S., & Weiss, S. M. (2013) · Physical Review B · doi:10.1103/physrevb.88.075307 · Cited by 13
Monolithically stackable hybrid FPGA
Strukov, D. B., & Mishchenko, A. (2010) · Design, Automation, and Test in Europe · doi:10.1109/date.2010.5457117 · Cited by 13
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3D-DPE: A 3D high-bandwidth dot-product engine for high-performance neuromorphic computing
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Metadata
- Authors
- Strukov, D. B., & Williams, R. S.
- Affiliations
- Hewlett-Packard (United States) (US)
- Venue
- Proceedings of the National Academy of Sciences
- Publisher
- National Academy of Sciences
- Published
- 2009-12
- Volume
- 106
- Issue
- 48
- Pages
- 20155-20158
- ISSN
- 0027-8424 (ISSN-L)
- 1091-6490
- PMC
- PMC2777961
- OpenAlex
- W2031176269
- Cited by
- 153
- References
- 27
- Citations by year
- 2026: 1 · 2025: 2 · 2024: 2 · 2023: 4 · 2022: 5 · 2021: 10 · 2020: 7 · 2019: 6 · 2018: 9 · 2017: 8 · 2016: 8 · 2015: 10 · 2014: 9 · 2013: 18 · 2012: 17
- FWCI
- 14.02
- Type
- journal article
- Language
- en
- Open access
- green
- www.ncbi.nlm.nih.gov
- Locations
- Proceedings of the National Academy of Sciences (publishedVersion)
- PubMed Central (publishedVersion)
- PubMed (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › 3D IC and TSV technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
- Keywords
- CMOS substrate, vertical interconnects, integration density, neuromorphic hardware
- MeSH terms
- Computer Systems, Electronics, Semiconductors, Electric Impedance
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Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
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