The DOI matches its Crossref record; 27 of the 27 references it cites were found in a registry or an index.
Four-dimensional address topology for circuits with stacked multilayer crossbar arrays
Open accessAbstract
We present a topological framework that provides a simple yet powerful electronic circuit architecture for constructing and using multilayer crossbar arrays, allowing a significantly increased integration density of memristive crosspoint devices beyond the scaling limits of lateral feature sizes. The truly remarkable feature of such circuits, which is an extension of the CMOL (Cmos + MOLecular-scale devices) concept for an area-like interface to a three-dimensional system, is that a large-feature-size complimentary metal-oxide-semiconductor (CMOS) substrate can provide high-density interconnects to multiple crossbar layers through a single set of vertical vias. The physical locations of the memristive devices are mapped to a four-dimensional logical address space such that unique access from the CMOS substrate is provided to every device in a stacked array of crossbars. This hybrid architecture is compatible with digital memories, field-programmable gate arrays, and biologically inspired adaptive networks and with state-of-the-art integrated circuit foundries.
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“Generally, Eq. (4) can be seen as a modification of the Duffing oscillator equation, whose chaotic properties are well-known 16 .”
From Bistable Nonvolatile Elastic-Membrane Memcapacitor Exhibiting a Chaotic Behavior (2011) · cites this paper as [16]
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Strukov, D. B., Snider, G. S., Stewart, D. R., & Williams, R. S. (2008) · Nature · doi:10.1038/nature06932 · Cited by 11,828
Self-citationMemristor—The Missing Circuit Element
Chua, L. (1971) · IEEE Transactions on Circuit Theory · doi:10.1109/tct.1971.1083337 · Cited by 10,268 · cited 1×
“Amemristorisa two-terminalelectricalcircuitelementthatchangesitsresistance dependingonthetotalamountofchargethatflowsthroughthe device(6,7).”
Nanoionics-based resistive switching memories
Waser, R., & Aono, M. (2007) · Nature Materials · doi:10.1038/nmat2023 · Cited by 4,923
Analog VLSI and Neural Systems
Mead, C. (1989) · CaltechAUTHORS (California Institute of Technology) · Cited by 2,776
Memristive devices and systems
Chua, L. O., & Kang, S. M. (1976) · Proceedings of the IEEE · doi:10.1109/proc.1976.10092 · Cited by 2,604 · cited 1×
“A memristor is a two-terminal electrical circuit element that changes its resistance depending on the total amount of charge that flows through the device (6, 7).”
BackgroundDevice scaling limits of Si MOSFETs and their application dependencies
Frank, D. J., Dennard, R. H., Nowak, E., Solomon, P. M., Taur, Y., & Wong, H. ‐. P. (2001) · Proceedings of the IEEE · doi:10.1109/5.915374 · Cited by 1,576
A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre
Green, J. E., Choi, J. W., Boukai, A. I., Bunimovich, Y. L., Johnston‐Halperin, E., DeIonno, E., Luo, Y., Sheriff, B. A., Xu, K., Shin, Y. S., et al. (2007) · Nature · doi:10.1038/nature05462 · Cited by 1,230
Electrical phenomena in amorphous oxide films
Dearnaley, G., Stoneham, A. M., & Morgan, D. V. (1970) · Reports on Progress in Physics · doi:10.1088/0034-4885/33/3/306 · Cited by 731
Memristor−CMOS Hybrid Integrated Circuits for Reconfigurable Logic
Xia, Q., Robinett, W., Cumbie, M. W., Banerjee, N., Cardinali, T. J., Yang, J. J., Wu, W., Li, X., Tong, W. M., Strukov, D. B., et al. (2009) · Nano Letters · doi:10.1021/nl901874j · Cited by 671
Self-citationNanoscale molecular-switch crossbar circuits
Chen, Y., Jung, G. Y., Ohlberg, D. A. A., Li, X., Stewart, D. R., Jeppesen, J. O., Nielsen, K. A., Stoddart, J. F., & Williams, R. S. (2003) · Nanotechnology · doi:10.1088/0957-4484/14/4/311 · Cited by 633
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Memristive devices for computing
Yang, J. J., Strukov, D. B., & Stewart, D. R. (2013) · Nature Nanotechnology · doi:10.1038/nnano.2012.240 · Cited by 3,885
Self-citationTraining and operation of an integrated neuromorphic network based on metal-oxide memristors
Prezioso, M., Merrikh-Bayat, F., Hoskins, B. D., Adam, G. C., Likharev, K. K., & Strukov, D. B. (2015) · Nature · doi:10.1038/nature14441 · Cited by 3,001
Self-citationKim, K.-H., Gaba, S., Wheeler, D., Cruz-Albrecht, J. M., Hussain, T., Srinivasa, N., & Lu, W. (2012) · Nano Letters · doi:10.1021/nl203687n · Cited by 924
Neuromorphic nanoelectronic materials
Sangwan, V. K., & Hersam, M. C. (2020) · Nature Nanotechnology · doi:10.1038/s41565-020-0647-z · Cited by 907
Memory effects in complex materials and nanoscale systems
Pershin, Y. V., & Di Ventra, M. (2011) · Advances In Physics · doi:10.1080/00018732.2010.544961 · Cited by 823
Metadata
- Authors
- Strukov, D. B., & Williams, R. S.
- Affiliations
- Hewlett-Packard (United States) (US)
- Venue
- Proceedings of the National Academy of Sciences
- Publisher
- National Academy of Sciences
- Published
- 2009-12
- Volume
- 106
- Issue
- 48
- Pages
- 20155-20158
- ISSN
- 0027-8424 (ISSN-L)
- 1091-6490
- PMC
- PMC2777961
- OpenAlex
- W2031176269
- Cited by
- 153
- References
- 27
- Citations by year
- 2026: 1 · 2025: 2 · 2024: 2 · 2023: 4 · 2022: 5 · 2021: 10 · 2020: 7 · 2019: 6 · 2018: 9 · 2017: 8 · 2016: 8 · 2015: 10 · 2014: 9 · 2013: 18 · 2012: 17
- FWCI
- 14.02
- Type
- journal article
- Language
- en
- Open access
- green
- www.ncbi.nlm.nih.gov
- Locations
- Proceedings of the National Academy of Sciences (publishedVersion)
- PubMed Central (publishedVersion)
- PubMed (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › 3D IC and TSV technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
- Keywords
- CMOS substrate, vertical interconnects, integration density, neuromorphic hardware
- MeSH terms
- Computer Systems, Electronics, Semiconductors, Electric Impedance
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