Cited by 25Analog and Mixed-Signal Circuit DesignNeuroscience and Neural EngineeringEEG and Brain-Computer Interfaces

Algorithm and hardware considerations for real-time neural signal on-implant processing

Open access
Zhang, Zheng, Savolainen, Oscar W, Constandinou, Timothy G·2022·Journal of Neural Engineering

Abstract

Abstract Objective. Various on-workstation neural-spike-based brain machine interface (BMI) systems have reached the point of in-human trials, but on-node and on-implant BMI systems are still under exploration. Such systems are constrained by the area and battery. Researchers should consider the algorithm complexity, available resources, power budgets, CMOS technologies, and the choice of platforms when designing BMI systems. However, the effect of these factors is currently still unclear. Approaches. Here we have proposed a novel real-time 128 channel spike detection algorithm and optimised it on microcontroller (MCU) and field programmable gate array (FPGA) platforms towards consuming minimal power and memory/resources. It is presented as a use case to explore the different considerations in system design. Main results. The proposed spike detection algorithm achieved over 97% sensitivity and a smaller than 3% false detection rate. The MCU implementation occupies less than 3 KB RAM and consumes 31.5 µ W ch −1 . The FPGA platform only occupies 299 logic cells and 3 KB RAM for 128 channels and consumes 0.04 µ W ch −1 . Significance. On the spike detection algorithm front, we have eliminated the processing bottleneck by reducing the dynamic power consumption to lower than the hardware static power, without sacrificing detection performance. More importantly, we have explored the considerations in algorithm and hardware design with respect to scalability, portability, and costs. These findings can facilitate and guide the future development of real-time on-implant neural signal processing platforms.

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Crossref · 10.1088/1741-2552/ac5268

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  • Power consumption is a significant concern in neural interface design, especially for battery-powered implantable applications, as it can impact implant lifetime and on-chip resources.

    “Power consumption is a significant concern in the design of neural interfaces, especially for battery-powered implantable applications, as it can impact the lifetime of the implants and the resources on-chip (Zhang et al., 2022).”

    From Comparative analysis of energy transfer mechanisms for neural implants (2024) · cites this paper as Zhang et al., 2022

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Authors
Zhang, Z., Savolainen, O. W., & Constandinou, T. G.
Affiliations
  • Imperial College London (GB)
  • University of Surrey (GB)
Corresponding author
Zhang, Zheng
Venue
Journal of Neural Engineering
Published
2022-02-01
Volume
19
Issue
1
Pages
016029
ISSN
  • 1741-2552 (ISSN-L)
  • 1741-2560
OpenAlex
W4210831940
Cited by
25
References
94
Citations by year
2025: 8 · 2024: 8 · 2023: 7 · 2022: 2
FWCI
1.82
Type
journal article
Language
en
Open access
Locations
  • Journal of Neural Engineering (publishedVersion, cc-by)
  • PubMed (publishedVersion)
Funders
  • Alzheimer's Society
  • University College London
  • UK Dementia Research Institute
  • Medical Research Council
  • Engineering and Physical Sciences Research Council (EP/M020975/1, EP/R024642/1, EP/N509486/1)
Topics
  • Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
  • Life Sciences › Neuroscience › Cellular and Molecular Neuroscience › Neuroscience and Neural Engineering
  • Life Sciences › Neuroscience › Cognitive Neuroscience › EEG and Brain-Computer Interfaces
Keywords
neural spike detection, brain-computer interface, microcontroller implementation, FPGA implementation, low-power hardware design, dynamic power consumption, algorithm-hardware co-design
MeSH terms
Algorithms, Computers, Humans, Signal Processing, Computer-Assisted, Brain-Computer Interfaces

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