A Low-Power Programmable Neural Spike Detection Channel With Embedded Calibration and Data Compression
Open accessAbstract
This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature extraction, and self-calibration functionalities. It can operate in two different output modes: 1) signal tracking, in which the neural signal is sampled and transmitted as raw data; and 2) feature extraction, in which the spikes of the neural signal are detected and encoded by piece-wise linear curves. Additionally, the channel offers a foreground calibration procedure in which the amplification gain and the passband of the embedded filter can be self-adjusted. The amplification stage obtains a noise efficiency factor of 2.16 and an input referred noise of 2.84 μVrms over a nominal bandwidth of 167 Hz-6.9 kHz. The channel includes a reconfigurable 8-bit analog-to-digital converter combined with a 3-bit controlled programmable gain amplifier for adjusting the input signal to the full scale range of the converter. This combined block achieves an overall energy consumption per conversion of 102 fJ at 90 kS/s. The energy consumed by the circuit elements which are strictly related to the digitization process is 14.12 fJ at the same conversion rate. The complete channel consumes 2.8 μW at 1.2 V voltage supply when operated in the signal tracking mode, and 3.1 μW when the feature extraction mode is enabled.
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On-chip signal processing, including spike detection and other data compression, is an emerging trend aimed at reducing transmitted data.
“Another emerging trend includes on-chip signal processing, such as spike detection [16, 54] or other forms of data compression [108, 132, 155] to reduce the amount of transmitted data.”
From Implantable neurotechnologies: a review of integrated circuit neural amplifiers (2016) · cites this paper as [108]
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- Authors
- Rodriguez-Perez, A., Ruiz-Amaya, J., Delgado-Restituto, M., & Rodriguez-Vazquez, Á.
- Venue
- IEEE Transactions on Biomedical Circuits and Systems
- Published
- 2012-04
- Volume
- 6
- Issue
- 2
- Pages
- 87-100
- ISSN
- 1932-4545 (ISSN-L)
- 1940-9990
- OpenAlex
- W2146216888
- Cited by
- 103
- References
- 40
- Citations by year
- 2025: 2 · 2024: 1 · 2023: 3 · 2022: 2 · 2021: 2 · 2020: 5 · 2019: 4 · 2018: 9 · 2017: 13 · 2016: 5 · 2015: 17 · 2014: 21 · 2013: 18 · 2012: 1
- FWCI
- 10.38
- Type
- journal article
- Language
- en
- Open access
- green
- idus.us.es
- Locations
- IEEE Transactions on Biomedical Circuits and Systems (publishedVersion)
- PubMed (publishedVersion)
- LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Científicas) (acceptedVersion, cc-by-nc-nd)
- DIGITAL.CSIC (Spanish National Research Council (CSIC)) (submittedVersion)
- idUS (Universidad de Sevilla) (submittedVersion, cc-by-nc-nd)
- Funders
- Universidad de Sevilla
- Ministerio de Ciencia e Innovación
- Junta de Andalucía
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Life Sciences › Neuroscience › Cellular and Molecular Neuroscience › Neuroscience and Neural Engineering
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Keywords
- neural spike detection, low-power CMOS circuit, programmable gain amplifier, data compression, noise efficiency factor, input-referred noise, signal tracking
- MeSH terms
- Action Potentials, Algorithms, Amplifiers, Electronic, Analog-Digital Conversion, Calibration, Fourier Analysis, Humans, Neurons, Neurophysiology, Electric Power Supplies, Data Compression
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