8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistors
Abstract
On-chip true random number generators (TRNG) have been gaining attention as an important component for building secure systems [1]. CMOS TRNGs typically exploit device-level noise, such as thermal or flicker noise to generate random bits [2]. Among various types of CMOS TRNGs, the meta-stability-based TRNG is known to have very high throughput for random bit generation, but it requires sophisticated control and calibration circuits to suppress bias [6]. Another popular type is the ring oscillator (RO)-based TRNG, which utilizes timing jitter [1-5]. Relatively simple circuits make it an attractive option, but there remains a need to improve the tolerance against power supply attacks and process/environmental variations [3]. Recently, selective use of a certain set of inverter chains based on pre-tuning was proposed to mitigate process variation effects [2].
Integrity signals
Registry
Cites
Statistics
Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
Si-CMOS-based tRNGs use circuitry with various types of entropy sources, such as timing jitter, chaotic maps, metastability, or noise jitter from SRAM bit-line leakages, for low power consumption.
“In contrast, Si-CMOS–based tRNGs use circuitry that uses various types of entropy sources, such as timing jitter, chaotic maps, metastability, or noise jitter from SRAM bit-line leakages for low power consumption.”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [19]
Those entropy sources rely on operation-induced variations.
“Note that those entropy sources rely on operation-induced variations (19–23).”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [19]
Si-CMOS-based tRNGs show excellent randomness and insensitivity to fabrication-induced variability.
“They show excellent randomness and insensitivity to fabrication-induced variability.”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [19]
Cites
Mathew, S. K., Srinivasan, S., Anders, M. A., Kaul, H., Hsu, S. K., Sheikh, F., Agarwal, A., Satpathy, S., & Krishnamurthy, R. K. (2012) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2012.2217631 · Cited by 195 · see citing works
The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators
Markettos, A. T., & Moore, S. W. (2009) · Lecture Notes in Computer Science · doi:10.1007/978-3-642-04138-9_23 · Cited by 192 · see citing works
16.3 A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS
Yang, K., Fick, D., Henry, M. B., Lee, Y., Blaauw, D., & Sylvester, D. (2014) · 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) · doi:10.1109/isscc.2014.6757434 · Cited by 155 · see citing works
True Random Number Generator circuits based on single- and multi-phase beat frequency detection
Tang, Q., Kim, B., Lao, Y., Parhi, K. K., & Kim, C. H. (2014) · Proceedings of the IEEE 2014 Custom Integrated Circuits Conference · doi:10.1109/cicc.2014.6946136 · Cited by 75 · see citing works
A robust −40 to 120°C all-digital true random number generator in 40nm CMOS
Yang, K., Blaauw, D. T., & Sylvester, D. (2015) · Symposium on VLSI Circuits · doi:10.1109/vlsic.2015.7231275 · Cited by 21 · see citing works
True hardware random number generation implemented in the 32-nm SOI POWER7+ processor
Liberty, J. S., Barrera, A., Boerstler, D., et al. (2013) · IBM Journal of Research and Development · doi:10.1147/jrd.2013.2279599 · Cited by 16 · see citing works
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL
Maneatis, J. G., Kim, J., McClatchie, I., et al. (2003) · Proceedings - ACM IEEE Design Automation Conference · doi:10.1145/775832.776006 · Cited by 14 · see citing works
Self-citation
Flagged first, then by citations
Cited by
Sorted by citations
Satpathy, S. K., Mathew, S. K., Kumar, R., Suresh, V., Anders, M. A., Kaul, H., Agarwal, A., Hsu, S., Krishnamurthy, R. K., & De, V. (2019) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2018.2886350 · Cited by 114 · see citing works
Taneja, S., Rajanna, V. K., & Alioto, M. (2021) · 2021 IEEE International Solid-State Circuits Conference (ISSCC) · doi:10.1109/isscc42613.2021.9366019 · Cited by 58 · see citing works
Wieczorek, P. Z., & Golofit, K. (2018) · IEEE Transactions on Circuits and Systems I: Regular Papers · doi:10.1109/tcsi.2017.2751144 · Cited by 53 · see citing works
Cryptographic transistor for true random number generator with low power consumption
Kim, S.-I., You, H.-J., Kim, M.-S., An, U.-S., Kim, M.-S., Lee, D. H., Ryu, S.-T., & Choi, Y.-K. (2024) · Science Advances · doi:10.1126/sciadv.adk6042 · Cited by 33 · see citing works
“This energy consumption outcome by the cryptoristor is comparable to those of other CMOS circuit-based tRNGs ( 19 – 23 ) and to those of non-CMOS–based tRNGs ( 11 – 18 ).”
- Authors
- Kim, E., Lee, M., & Kim, J.-J.
- Affiliations
- Pohang University of Science and Technology (KR)
- Venue
- 2017 IEEE International Solid-State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Published
- 2017-02
- Pages
- 144-145
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W2594309104
- Cited by
- 79
- References
- 7
- Citations by year
- 2026: 5 · 2025: 6 · 2024: 8 · 2023: 9 · 2022: 12 · 2021: 11 · 2020: 12 · 2019: 7 · 2018: 6 · 2017: 3
- FWCI
- 5.44
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
- Open Access System for Information Sharing (Pohang University of Science and Technology) (submittedVersion)
- Funders
- IC Design Education Center
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Physical Unclonable Functions (PUFs) and Hardware Security
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Keywords
- true random number generator, ring oscillator, differential ring oscillator, feedback resistor, 65 nm CMOS, timing jitter, process variation tolerance, energy efficiency
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review