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Cited by 155Physical Unclonable Functions (PUFs) and Hardware SecurityLow-power high-performance VLSI designAnalog and Mixed-Signal Circuit Design

16.3 A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS

Yang, Kaiyuan, Fick, David, Henry, Michael B., Lee, Yoonmyung, Blaauw, David, Sylvester, Dennis·2014·2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
DOI 10.1109/isscc.2014.6757434
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Abstract

True random number generators (TRNGs) use physical randomness as entropy sources and are heavily used in cryptography and security [1]. Although hardware TRNGs provide excellent randomness, power consumption and design complexity are often high. Previous work has demonstrated TRNGs based on a resistor-amplifier-ADC chain [2], oscillator jitter [1], metastability [3-5] and other device noise [6-7]. However, analog designs suffer from variation and noise, making them difficult to integrate with digital circuits. Recent metastability-based methods [3-5] provide excellent performance but often require careful calibration to remove bias. SiN MOSFETs [6] exploit larger thermal noise but require post-processing to achieve sufficient randomness. An oxide breakdown-based TRNG [7] shows high entropy but suffers from low performance and high energy/bit. Ring oscillator (RO)-based TRNGs offer the advantage of design simplicity, but previous methods using a slow jittery clock to sample a fast clock provide low randomness [1] and are vulnerable to power supply attacks [8]. In addition, the majority of previous methods cannot pass all NIST randomness tests.

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  • TRNGs using phase jitter extract entropy from edge-jitter of an oscillator and sample jitter events using a phase detector, including ring oscillators, coupled oscillators and Fibonacci/Galois ring oscillators.

    “These TRNGs extract entropy from edge-jitter of oscillator and sample jitter events using phasedetector, including ring oscillators [7], coupled oscillators [2], [22], [23] and Fibonacci/Galois ring oscillators [24], [25].”

    From True Random Number Generators Using Electrical Noise (2019) · cites this paper as [7]

  • All prior true random number generators have suffered from drawbacks in scalability, circuit complexity, or reliance on post-processing such as a Von Neumann corrector to remove bias.

    “However, all prior TRNGs have suffered from drawbacks in scalability, circuit complexity, or relied on post-processing such as a “Von Neumann corrector” to remove bias from the generated bit sequences4–13.”

    From A novel true random number generator based on a stochastic diffusive memristor (2017) · cites this paper as [10]

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Authors
Yang, K., Fick, D., Henry, M. B., Lee, Y., Blaauw, D., & Sylvester, D.
Affiliations
University of Michigan (US)
ORCID
Venue
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Publisher
IEEE
Published
2014-02
Pages
280-281
ISSN
0193-6530 (ISSN-L)
DOI
10.1109/isscc.2014.6757434
OpenAlex
W1990478559
Cited by
155
References
8
Citations by year
2026: 5 · 2025: 16 · 2024: 15 · 2023: 11 · 2022: 18 · 2021: 14 · 2020: 18 · 2019: 16 · 2018: 10 · 2017: 13 · 2016: 11 · 2015: 6 · 2014: 2
FWCI
6.96
Type
conference paper
Language
en
Open access
closed
Locations
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
Topics
  • Physical Sciences › Computer Science › Hardware and Architecture › Physical Unclonable Functions (PUFs) and Hardware Security
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
  • Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
Keywords
true random number generator, 28nm CMOS, 65 nm CMOS, ring oscillator, NIST randomness tests, device noise

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