The DOI matches its Crossref record; 18 of the 18 references it cites were found in a registry or an index.
Nano/CMOS architectures using a field-programmable nanowire interconnect
Open accessAbstract
A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's law without having to shrink the transistors. Compilation of standard benchmark circuits onto FPNI chip models shows reduced area (8 × to 25 × ), reduced power, slightly lower clock speeds, and high defect tolerance—an FPNI chip with 20% defective junctions and 20% broken nanowires has an effective yield of 75% with no significant slowdown along the critical path, compared to a defect-free chip. Simulations show that the density and power improvements continue as both CMOS and nano fabrication parameters scale down, although the maximum clock rate decreases due to the high resistance of very small (<10 nm) metallic nanowires.
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Cites
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Cited by
Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges
Waser, R., Dittmann, R., Staikov, G., & Szot, K. (2009) · Advanced Materials · doi:10.1002/adma.200900375 · Cited by 5,080
Nanoionics-based resistive switching memories
Waser, R., & Aono, M. (2007) · Nature Materials · doi:10.1038/nmat2023 · Cited by 4,923
Memristive devices for computing
Yang, J. J., Strukov, D. B., & Stewart, D. R. (2013) · Nature Nanotechnology · doi:10.1038/nnano.2012.240 · Cited by 3,885
Memristor−CMOS Hybrid Integrated Circuits for Reconfigurable Logic
Xia, Q., Robinett, W., Cumbie, M. W., Banerjee, N., Cardinali, T. J., Yang, J. J., Wu, W., Li, X., Tong, W. M., Strukov, D. B., et al. (2009) · Nano Letters · doi:10.1021/nl901874j · Cited by 671
Self-citationHigh-Density Crossbar Arrays Based on a Si Memristive System
Jo, S. H., Kim, K.-H., & Lu, W. (2009) · Nano Letters · doi:10.1021/nl8037689 · Cited by 574
Metadata
- Authors
- Snider, G. S., & Williams, R. S.
- Venue
- Nanotechnology
- Publisher
- IOP Publishing
- Published
- 2007-01-03
- Volume
- 18
- Issue
- 3
- Pages
- 035204
- ISSN
- 0957-4484 (ISSN-L)
- 1361-6528
- OpenAlex
- W2111173832
- Cited by
- 364
- References
- 18
- FWCI
- 42.52
- Type
- journal article
- Language
- en
- Open access
- bronze
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