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High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm
Open accessAbstract
Using memristive properties common for titanium dioxide thin film devices, we designed a simple write algorithm to tune device conductance at a specific bias point to 1% relative accuracy (which is roughly equivalent to seven-bit precision) within its dynamic range even in the presence of large variations in switching behavior. The high precision state is nonvolatile and the results are likely to be sustained for nanoscale memristive devices because of the inherent filamentary nature of the resistive switching. The proposed functionality of memristive devices is especially attractive for analog computing with low precision data. As one representative example we demonstrate hybrid circuitry consisting of an integrated circuit summing amplifier and two memristive devices to perform the analog multiply-and-add (dot-product) computation, which is a typical bottleneck operation in information processing.
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“To program an RRAM cell to its target conductance, we use an incremental-pulse write–verify technique42.”
From A compute-in-memory chip based on resistive random-access memory (2022) · cites this paper as [42]
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Cited by
Sorted by citations
Items 101–200 of 557
A Memristor SPICE Model Accounting for Volatile Characteristics of Practical ReRAM
Berdan, R., Lim, C. K. K., Khiat, A., Papavassiliou, C., & Prodromakis, T. (2014) · IEEE Electron Device Letters · doi:10.1109/led.2013.2291158 · Cited by 71
“threshold, where resistance switching is a function of applied voltage, pulse width and interpulse timing [12]–[13].”
BackgroundUnderstanding the Dual Nature of the Filament Dissolution in Conductive Bridging Devices
Celano, U., Goux, L., Belmonte, A., Opsomer, K., Degraeve, R., Detavernier, C., Jurczak, M., & Vandervorst, W. (2015) · The Journal of Physical Chemistry Letters · doi:10.1021/acs.jpclett.5b00633 · Cited by 71
Kim, H. J., Baek, Y.-J., Choi, Y. J., Kang, C. J., Lee, H. H., Kim, H.-M., Kim, K. B., & Yoon, T. (2013) · RSC Advances · doi:10.1039/c3ra42683a · Cited by 70
HfO x /AlO y Superlattice‐Like Memristive Synapse
Wang, C., Mao, G., Huang, M., Huang, E., Zhang, Z., Yuan, J., Cheng, W., Xue, K., Wang, X., & Miao, X. (2022) · Advanced Science · doi:10.1002/advs.202201446 · Cited by 70
Guo, X., Merrikh-Bayat, F., Gao, L., Hoskins, B. D., Alibart, F., Linares-Barranco, B., Theogarajan, L. S., Teuscher, C., & Strukov, D. B. (2015) · Frontiers in Neuroscience · doi:10.3389/fnins.2015.00488 · Cited by 69
“A related issue might be measurement noise upon reading the state of the memristor, e.g., due to the fluctuations in the device conductance over time, which is sometimes observed as random telegraph noise (Gao et al., 2012, 2013b; Prezioso et al., 2015b).”
BackgroundMethodInfluentialSelf-citationJang, J., Gi, S., Yeo, I., Choi, S., Jang, S., Ham, S., Lee, B., & Wang, G. (2022) · Advanced Science · doi:10.1002/advs.202201117 · Cited by 68
Low Bit-Width Convolutional Neural Network on RRAM
Cai, Y., Tang, T., Xia, L., Li, B., Wang, Y., & Yang, H. (2019) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2019.2917852 · Cited by 68
“On the one hand, the resistance level of the RRAM device cannot support the available storage of high-precision data [13].”
BackgroundKim, K., Song, M. S., Hwang, H., Hwang, S., & Kim, H. (2024) · Frontiers in Neuroscience · doi:10.3389/fnins.2024.1279708 · Cited by 72
“This tuning algorithm is designed to approach the target conductance as closely as possible by employing read pulses between switching voltage pulses (Alibart et al., 2012; Kim H. et al., 2021).”
MethodCoexistence of analog and digital resistive switching in BiFeO3-based memristive devices
Shi, T., Yang, R., & Guo, X. (2016) · Solid State Ionics · doi:10.1016/j.ssi.2016.09.001 · Cited by 68
TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks
Cheng, M., Xia, L., Zhu, Z., Cai, Y., Xie, Y., Wang, Y., & Yang, H. (2018) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2018.2824304 · Cited by 67
“Recent work has proved RRAM device in crossbar can represent 5-bit data [24].”
BackgroundA Memristor-Based Optimization Framework for Artificial Intelligence Applications
Liu, S., Wang, Y., Fardad, M., & Varshney, P. K. (2018) · IEEE Circuits and Systems Magazine · doi:10.1109/mcas.2017.2785421 · Cited by 69
“In addition to circuit-level techniques [19], [27], [28], [51], we will show that the non-ideal effects caused by hardware variations can also be mitigated by optimizing the algorithm prior to mapping to memristor crossbars.”
BackgroundMethodA Fault-Tolerant Neural Network Architecture
Liu, T., Wen, W., Jiang, L., Wang, Y., Yang, C., & Quan, G. (2019) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1145/3316781.3317742 · Cited by 66
“We simulate a memristive accelerator similar to [9], wherein each layer of selected neural network model is mapped to one or more 128×128 arrays and each memristive cell maintains 64 quantization levels (6-bit) to achieve a good balance between throughput and reliability [2].”
MethodPhenomenological modeling of memristive devices
Bayat, F. M., Hoskins, B. D., & Strukov, D. B. (2015) · Applied Physics A · doi:10.1007/s00339-015-8993-7 · Cited by 61
Self-citationIMAGING: In-Memory AlGorithms for Image processiNG
Haj-Ali, A., Ben-Hur, R., Wald, N., Ronen, R., & Kvatinsky, S. (2018) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2018.2846699 · Cited by 63
“The input multipliers are represented as voltage while the multiplicands are stored as resistances in multi-level cells (MLC) [32]–[35].”
BackgroundA Robust 8-Bit Non-Volatile Computing-in-Memory Core for Low-Power Parallel MAC Operations
Zhang, S., Huang, K., & Shen, H. (2020) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2020.2971642 · Cited by 62
“As reported in RRAM devices, different reading voltages will cause 0% to 40% resistance deviations, and some even exceed 50% in LRS [10], [12], [13], [30], [39].”
BackgroundInfluentialBousoulas, P., Michelakaki, I., Skotadis, E., Tsigkourakos, M., & Tsoukalas, D. (2017) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2017.2709338 · Cited by 57
An Ultra Low-Power Memristive Neuromorphic Circuit for Internet of Things Smart Sensors
Fayyazi, A., Ansari, M., Kamal, M., Afzali‐Kusha, A., & Pedram, M. (2018) · IEEE Internet of Things Journal · doi:10.1109/jiot.2018.2799948 · Cited by 56
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration
Nag, A., Balasubramonian, R., Srikumar, V., Walker, R. M., Shafiee, A. R., Strachan, J. P., & Muralimanohar, N. (2018) · IEEE Micro · doi:10.1109/mm.2018.053631140 · Cited by 55
A Parallel Multibit Programing Scheme With High Precision for RRAM-Based Neuromorphic Systems
Chen, J.-R., Wu, H., Gao, B., Tang, J., Hu, X. S., & Qian, H. (2020) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2020.2979606 · Cited by 55
“Although the traditional incremental step pulse programing (ISPP) scheme has the potential for row-by-row programing on the 1-transistor-1-RRAM (1T1R) arrays, the studies for fast convergence of the conductance tuning is still based on stand-alone single cells [6], [7].”
BackgroundReview of radiation effects on ReRAM devices and technology
Gonzalez-Velo, Y., Barnaby, H., & Kozicki, M. N. (2017) · Semiconductor Science and Technology · doi:10.1088/1361-6641/aa6124 · Cited by 55
High precision analogue memristor state tuning
Berdan, R., Prodromakis, T., & Toumazou, C. (2012) · Electronics Letters · doi:10.1049/el.2012.2295 · Cited by 53
Time Complexity of In-Memory Solution of Linear Systems
Sun, Z., Pedretti, G., Mannocci, P., Ambrosi, E., Bricalli, A., & Ielmini, D. (2020) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2020.2992435 · Cited by 58
“To guarantee that the minimal eigenvalue is in the vicinity of the ideal one and, thus, the computing time is predictable, it is important to reduce device variations by using devices of large conductance window accommodating sufficient analog levels, also by using verify algorithms for device programming [20].”
MethodPrezioso, M., Kataeva, I., Merrikh‐Bayat, F., Hoskins, B. D., Adam, G. C., Sota, T., Likharev, K. K., & Strukov, D. B. (2015) · Technical digest - International Electron Devices Meeting/Technical digest · doi:10.1109/iedm.2015.7409719 · Cited by 51
Self-citationDot-product engine as computing memory to accelerate machine learning algorithms
Hu, M., Strachan, J. P., Li, Z., Stanley, R., & Williams (2016) · International Symposium on Quality Electronic Design (ISQED) · doi:10.1109/isqed.2016.7479230 · Cited by 52
“Feedback approaches can lead to nearly arbitrarily high accuracy of the memristor states with the cost of increased programming time [16].”
BackgroundManhattan rule training for memristive crossbar circuit pattern classifiers
Zamanidoost, E., Bayat, F. M., Strukov, D. B., & Kataeva, I. (2015) · IEEE International Symposium on Intelligent Signal Processing, · doi:10.1109/wisp.2015.7139171 · Cited by 48
“Such analog adjustment of weights is possible (e.g. using feedback write algorithm [17]) and could be reasonable for small circuits [1], but would certainly be too slow for the desired large-scale circuits, especially taking into account that large number of epochs is typically required to perform…”
BackgroundSelf-citationA Precise Algorithm of Memristor Switching to a State with Preset Resistance
Nikiruy, K. E., Emelyanov, A. V., Demin, V. A., Rylkov, V. V., Ситников, А. В., & Kashkarov, P. K. (2018) · Technical Physics Letters · doi:10.1134/s106378501805022x · Cited by 49
Accurate Inference With Inaccurate RRAM Devices: A Joint Algorithm-Design Solution
Charan, G., Mohanty, A., Du, X., Krishnan, G., V, Joshi, R., & Cao, Y. K. (2020) · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits · doi:10.1109/jxcdc.2020.2987605 · Cited by 48
“5 µ s–4.5 ms, whereas SRAM write takes ∼ 1 ns [13].”
BackgroundInfluentialRedesigning commercial floating-gate memory for analog computing applications
Bayat, F. M., Guo, X., Om'mani, H. A., Do, N., Likharev, K. K., & Strukov, D. B. (2015) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2015.7169048 · Cited by 47
“The tuning procedure stops when the device has reached the desired analog state with the pre-specified precision [22, 23].”
BackgroundMethodSelf-citationEndurance-write-speed tradeoffs in nonvolatile memories
Strukov, D. B. (2016) · Applied Physics A · doi:10.1007/s00339-016-9841-0 · Cited by 47
Self-citationGraves, C. E., Dávila, N., Grafals, E. M., Lam, S., Strachan, J. P., & Williams, R. S. (2017) · Applied Physics Letters · doi:10.1063/1.4978757 · Cited by 46
Andrulis, T., Emer, J., & Sze, V. (2023) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1145/3579371.3589062 · Cited by 54
“ReRAMs have been shown to be programmable with up to 5b [1] and 512 × 512 crossbars have been shown to compute up to 8b column sums [17] under analog noise limitations.”
MethodVariation-tolerant Computing with Memristive Reservoirs
Bürger, J., & Teuscher, C. (2013) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1109/nanoarch.2013.6623028 · Cited by 46
“In [10] an algorithm was presented that allows high precision tuning of memristors.”
MethodKim, S., Lee, Y., Kim, H., & Choi, S. (2019) · Nanoscale · doi:10.1039/c9nr08979a · Cited by 46
Neuron Circuits for Low-Power Spiking Neural Networks Using Time-To-First-Spike Encoding
Oh, S., Kwon, D., Yeom, G., Kang, W.-M., Lee, S., Woo, S. Y., Kim, J., & Lee, J. (2022) · IEEE Access · doi:10.1109/access.2022.3149577 · Cited by 51
“For example, device-todevice variation can be reduced by precision tuning using the read-write-verify scheme in the weight transfer process [51].”
MethodDesign of Power- and Variability-Aware Nonvolatile RRAM Cell Using Memristor as a Memory Element
Pal, S., Bose, S., Ki, W., & Islam, A. (2019) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2019.2928830 · Cited by 45
“The need for multiple-cycle write-verify programming scheme, undesired drift in programmed resistance due to aging, as well as limited endurance of memristor devices are some of the limitations that plague memristor-based cells [41].”
BackgroundDai, G., Huang, T., Wang, Y., Yang, H., & Wawrzynek, J. (2019) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1145/3287624.3287637 · Cited by 44
“The emergingmetal-oxide resistive random accessmemory (ReRAM) and ReRAM crossbars show huge potential in energy efficient processing-in-memory operations [15, 16], especially for matrixvector multiplications [17].”
BackgroundGonzales, C., Bou, A., Guerrero, A., & Bisquert, J. (2024) · The Journal of Physical Chemistry Letters · doi:10.1021/acs.jpclett.4c00945 · Cited by 43
Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors
Hoe, D. H. K., Rajendran, J., & Karri, R. (2014) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi.2014.50 · Cited by 43
“Experimental results presented by [23] have demonstrated the effectiveness of a simple feedback algorithm for tuning the resistance of a memristor to 1% relative accuracy at the microscale although scaling analysis by [24] suggests this can be extended to the nanoscale.”
BackgroundComplex Learning in Bio-plausible Memristive Networks
Deng, L., Li, G., Deng, N., Wang, D., Zhang, Z., He, W., Li, H., Pei, J., & Shi, L. (2015) · Scientific Reports · doi:10.1038/srep10684 · Cited by 43
“We can further tune the weight value to achieve a higher precision by introducing the feedback modulating algorithm 39,57 at the cost of longer modulation time.”
Charan, G., Hazra, J., Beckmann, K., Du, X., Krishnan, G., V, Joshi, R., Cady, N. C., & Cao, Y. K. (2020) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1109/dac18072.2020.9218605 · Cited by 43
“5 ms , whereas SRAM write takes ∼ 1 ns [7].”
BackgroundAnalog-input analog-weight dot-product operation with Ag/a-Si/Pt memristive devices
Gao, L., Alibart, F., & Strukov, D. B. (2012) · IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC) · doi:10.1109/vlsi-soc.2012.7332082 · Cited by 41
Self-citationRandom sparse adaptation for accurate inference with inaccurate multi-level RRAM arrays
Mohanty, A., Du, X., Chen, P.-Y., Seo, J.-S., Yu, S., & Cao, Y. K. (2017) · Technical digest - International Electron Devices Meeting/Technical digest · doi:10.1109/iedm.2017.8268339 · Cited by 42
Gao, L., Merrikh-Bayat, F., Alibart, F., Guo, X., Hoskins, B. D., Cheng, K.-T. T., & Strukov, D. B. (2013) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1109/nanoarch.2013.6623031 · Cited by 41
Self-citationAdaptive Weight Quantization Method for Nonlinear Synaptic Devices
Kwon, D., Lim, S., Bae, J., Lee, S., Kim, H., Kim, C.-H., Park, B., & Lee, J. (2018) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2018.2879821 · Cited by 41
“In the case of RRAM, the conductance is set to the desired value with 1% error by transforming the shape of pulse applied to the device [16].”
Method3D CMOS-memristor hybrid circuits
Cheng, K.-T. T., & Strukov, D. B. (2012) · International Symposium on Physical Design · doi:10.1145/2160916.2160925 · Cited by 40
“The very structure of CMOL circuits makes them uniquely suited for the implementation of ultrafast ANN [14] [37] and, in general, mixed-signal information processing systems [42] [41] .”
BackgroundSelf-citationAEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs
Tang, S., Yin, S., Zheng, S., Ouyang, P., Tu, F., Yao, L., Wu, J., Cheng, W., Liu, L., & Wei, S. (2017) · IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) · doi:10.1109/nvmsa.2017.8064475 · Cited by 40
“Because the resolution of the state-of-the-art RRAM cell [18][12][13] (e.”
BackgroundExperimental study of LiNbO3 memristors for use in neuromorphic computing
Wang, S., Wang, W., Yakopcic, C., Shin, E., Subramanyam, G., & Taha, T. M. (2016) · Microelectronic Engineering · doi:10.1016/j.mee.2016.10.007 · Cited by 39
Analog resistive switching behavior of Al/Nb2O5/Al device
Mähne, H., Wylezich, H., Hanzig, F., Slesazeck, S., Rafaja, D., & Mikolajick, T. (2014) · Semiconductor Science and Technology · doi:10.1088/0268-1242/29/10/104002 · Cited by 38
Electrode-material dependent switching in TaOxmemristors
Ge, N., Zhang, M.-X., Zhang, L., Yang, J. J., Li, Z., & Williams, R. S. (2014) · Semiconductor Science and Technology · doi:10.1088/0268-1242/29/10/104003 · Cited by 38
Luo, Y., Han, X., Ye, Z., Barnaby, H., Seo, J.-S., & Yu, S. (2020) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2020.3015940 · Cited by 37
“The second is through the write–verify-based programming scheme [6]–[9].”
BackgroundOverview of Memristor-Based Neural Network Design and Applications
Ye, L., Gao, Z., Fu, J., Ren, W., Yang, C., Wen, J., Wan, X., Ren, Q., Gu, S., Liu, X., et al. (2022) · Frontiers in Physics · doi:10.3389/fphy.2022.839243 · Cited by 40
“Several innovative approaches have been proposed to address these drawbacks, such as doping and dislocation [144], using two series memristors and a minimum size transistor to encode the resistance ratio of a memristor [145], and a closed-loop peripheral circuit with a write-verify function [146].”
BackgroundResistive GP-SIMD Processing-In-Memory
Morad, A., Yavits, L., Kvatinsky, S., & Ginosar, R. (2016) · ACM Transactions on Architecture and Code Optimization · doi:10.1145/2845084 · Cited by 36
Model-based high-precision tuning of NOR flash memory cells for analog computing applications
Bayat, F. M., Guo, X., Klachko, M., Do, N., Likharev, K. K., & Strukov, D. B. (2016) · Conference digest · doi:10.1109/drc.2016.7548449 · Cited by 36
Self-citationAbdurahman, A., Jiang, H., & Hu, C. (2017) · Journal of the Franklin Institute · doi:10.1016/j.jfranklin.2017.08.013 · Cited by 36
Mikhaylov, A. N., Pigareva, Y., Pimashkin, A. S., Lobov, S. A., Kazantsev, V., Морозов, О. А., Ovchinnikov, P. E., Antonov, I. N., Belov, A. I., Korolev, D. S., et al. (2018) · IEEE Transactions on Emerging Topics in Computational Intelligence · doi:10.1109/tetci.2018.2829922 · Cited by 37
“Special adaptive programming algorithms can be also used to reduce the resistance variations [51], but at the cost”
MethodCao, Y., Zhao, T., Zhao, C., Liu, Y., Song, P., Gao, H., & Zhao, C. (2022) · Journal of Materials Chemistry C · doi:10.1039/d1tc04827a · Cited by 36
Nanoscale Conductive Filament with Alternating Rectification as an Artificial Synapse Building Block
Berco, D., Zhou, Y., Gollu, S. R., Kalaga, P. S., Kole, A., Hassan, M. Y., & Ang, D. S. (2018) · ACS Nano · doi:10.1021/acsnano.8b02193 · Cited by 35
Gomez, J. T., Vourkas, I., & Hoffman, A. C. A. (2019) · IEEE Access · doi:10.1109/access.2019.2915100 · Cited by 35
“5k according to algorithm proposed in [31].”
Memristive Electronic Synapses Made by Anodic Oxidation
Chen, S., Noori, S., Villena, M. A., Shi, Y., Han, T., Zuo, Y., Pedeferri, M., Strukov, D. B., Lanza, M., & Diamanti, M. V. (2019) · Chemistry of Materials · doi:10.1021/acs.chemmater.9b02245 · Cited by 34
“3,50 More importantly, the implementation of gradual conductance changes has been also achieved by applying sequences of ac training pulses.”
BackgroundSelf-citationPedretti, G., Ambrosi, E., & Ielmini, D. (2021) · 2021 IEEE International Reliability Physics Symposium (IRPS) · doi:10.1109/irps46558.2021.9405130 · Cited by 39
“I, namely (a) multilevel [19], [20], (b) binary [26], (c) unary [27], (d) multilevel with redundancy [28] and (e) slicing [29].”
BackgroundKura, C., Aoki, Y., Tsuji, E., Habazaki, H., & Martin, M. (2016) · RSC Advances · doi:10.1039/c5ra21160c · Cited by 34
Merrikh-Bayat, F., Merrikh‐Bayat, F., & Shouraki, S. B. (2013) · IEEE Transactions on Fuzzy Systems · doi:10.1109/tfuzz.2013.2290140 · Cited by 33
“ristive device is a nonlinear element whose resistance (known as memristance) can be tuned to a value between Ron and Roff by applying a suitable voltage to the device [26], [27].”
BackgroundZhang, L., Strukov, D. B., Saadeldeen, H., Fan, D., Zhang, M., & Franklin, D. M. (2014) · International Conference on Parallel Architectures and Compilation Techniques (PACT) · doi:10.1145/2628071.2628081 · Cited by 33
“This variable-precision storage, projected to be up to seven bits[3] in a single memristor bit, is a perfect match to meet the requirement of different directory storage requirements in different situations—For situations where directory entries are many but each with few sharers, we use additional memristor levels to…”
BackgroundMethodInfluentialSelf-citationFlexible memristor based neuromorphic system for implementing multi-layer neural network algorithms
Yakopcic, C., Hasan, R., & Taha, T. M. (2017) · International Journal of Parallel Emergent and Distributed Systems · doi:10.1080/17445760.2017.1321761 · Cited by 33
“It was assumed that memristors only have 128 discernible states in their resistance range [58].”
BackgroundInfluentialWang, C., Feng, D., Tong, W., Liu, J., Li, Z., Chang, J., Zhang, Y., Wu, B., Xu, J., Zhao, W. J., et al. (2019) · ACM Transactions on Design Automation of Electronic Systems · doi:10.1145/3325067 · Cited by 34
“Multilevel states can be achieved by varying the pulse amplitude, pulse width, pulse number, or a combination of them [3, 215].”
BackgroundMethodInfluentialSahay, S., Bavandpour, M., Mahmoodi, M. R., & Strukov, D. B. (2020) · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits · doi:10.1109/jxcdc.2020.2981048 · Cited by 36
“Previous works have already shown an effective weight precision greater than 7-bits based on a simple tuning algorithm [19].”
BackgroundSelf-citationSpara: An Energy-Efficient ReRAM-Based Accelerator for Sparse Graph Analytics Applications
Zheng, L., Zhao, J., Huang, Y., Wang, Q., Zeng, Z., Xue, J., Liao, X., & Jin, H. (2020) · IEEE International Parallel and Distributed Processing Symposium (IPDPS) · doi:10.1109/ipdps47924.2020.00077 · Cited by 33
“We can use Shift and Add (S/A) to generate expected resolution based on the low-resolution solutions [25], [26].”
BackgroundMethodHigh Amplitude Spike Generator in Au Nanodot-Incorporated NbOx Mott Memristor
Park, W., Kim, G., In, J. H., Rhee, H., Song, H., Park, J., Martinez, A., & Kim, K. M. (2023) · Nano Letters · doi:10.1021/acs.nanolett.2c04599 · Cited by 34
Memristive devices as parameter setting elements in programmable gain amplifiers
Berdan, R., Prodromakis, T., Salaoru, I., Khiat, A., & Toumazou, C. (2012) · Applied Physics Letters · doi:10.1063/1.4770315 · Cited by 32
Flexible Parylene C-Based RRAM Array for Neuromorphic Applications
Kim, J.-E., Kim, B., Kwon, H. T., Kim, J.-S., Kim, K., Park, D., & Kim, Y. (2022) · IEEE Access · doi:10.1109/access.2022.3211956 · Cited by 32
“Several memory devices such as static random access memory (RAM), phase-change memory, spin-transfer torque RAM, floating gate memory, charge trap flash memory, and resistive RAM (RRAM) have been proposed to emulate the functionalities of synapses [5], [6], [7], [8], [9], [10].”
BackgroundKim, J.-D., Baek, Y.-J., Choi, Y. J., Kang, C. J., Lee, H. H., Kim, H.-M., Kim, K. B., & Yoon, T. (2013) · Journal of Applied Physics · doi:10.1063/1.4846759 · Cited by 32
Memristor Crossbar Array with Enhanced Device Yield for In-Memory Vector–Matrix Multiplication
Kim, T., Kim, S., Park, J., Youn, S., & Kim, H. (2024) · ACS Applied Electronic Materials · doi:10.1021/acsaelm.4c00199 · Cited by 31
Resistance-Restorable Nanofluidic Memristor and Neuromorphic Chip
Liu, K., Wang, Y., Sun, M., Lu, J., Shi, D., & Xie, Y. (2025) · Nano Letters · doi:10.1021/acs.nanolett.5c00315 · Cited by 34
Dynamical attractors of memristors and their networks
Pershin, Y. V., & Slipko, V. A. (2019) · Europhysics Letters (EPL) · doi:10.1209/0295-5075/125/20002 · Cited by 31
Combinatorial optimization by weight annealing in memristive hopfield networks
Fahimi, Z., Mahmoodi, M. R., Nili, H., Polishchuk, V., & Strukov, D. B. (2021) · Scientific Reports · doi:10.1038/s41598-020-78944-5 · Cited by 35
Self-citationOrigin of the OFF state variability in ReRAM cells
Salaoru, I., Khiat, A., Li, Q., Berdan, R., Papavassiliou, C., & Prodromakis, T. (2014) · Journal of Physics D Applied Physics · doi:10.1088/0022-3727/47/14/145102 · Cited by 31
Using Memristors for Robust Local Learning of Hardware Restricted Boltzmann Machines
Ernoult, M., Grollier, J., & Querlioz, D. (2019) · Scientific Reports · doi:10.1038/s41598-018-38181-3 · Cited by 33
Recent Progress on Memristive Convolutional Neural Networks for Edge Intelligence
Qin, Y., Bao, H., Wang, F., Chen, J., Li, Y., & Miao, X. (2020) · Advanced Intelligent Systems · doi:10.1002/aisy.202000114 · Cited by 37
Analog Weight Updates with Compliance Current Modulation of Binary ReRAMs for On-Chip Learning
Payvand, M., Demirağ, Y., Dalgaty, T., Vianello, E., & Indiveri, G. (2020) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas45731.2020.9180808 · Cited by 27
“Also, tuning the precise memory state is not always easily achievable in a real-time manner, requiring recursively tuning with an active feedback scheme [7], [8].”
BackgroundEffect of Program Error in Memristive Neural Network With Weight Quantization
Kim, T., Kim, S., Hong, K., Park, J., Youn, S., Lee, J., Park, B., & Kim, H. (2022) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2022.3169112 · Cited by 30
Nourazar, M., Rashtchi, V., Azarpeyvand, A., & Merrikh‐Bayat, F. (2018) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2018.2837908 · Cited by 30
“1) DAC and ADC Converters: Since the maximum precision for tuning memristors is 6 or 7 bits [22], [41], a simple”
BackgroundNeuADC: Neural Network-Inspired Synthesizable Analog-to-Digital Conversion
Cao, W., He, X. J., Chakrabarti, A., & Zhang, X. (2019) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2019.2925391 · Cited by 29
“Previous work has employed 6–12-bit RRAM precision for RRAM-based NN computation [14], [15], [38], [45].”
MethodLi, J., Duan, Q., Zhang, T., Yin, M., Sun, X., Cai, Y., Li, L., Yang, Y., & Huang, R. (2017) · RSC Advances · doi:10.1039/c7ra07522g · Cited by 29
A Novel ReRAM-Based Processing-in-Memory Architecture for Graph Traversal
Han, L., Shen, Z., Liu, D., Shao, Z., Huang, H. H., & Li, T. (2018) · ACM Transactions on Storage · doi:10.1145/3177916 · Cited by 28
“Moreover, considering the fact that the size of cells keeps shrinking, multi-level cell (MLC) technology enables one ReRAM cell to store more information [4, 33, 48], which is suitable as a storage device to store large-scale graphs.”
BackgroundMethodArtificial neural networks based on memristive devices
Ravichandran, V., Li, C., BanaGozar, A., Yang, J. J., & Xia, Q. (2018) · Science China Information Sciences · doi:10.1007/s11432-018-9425-1 · Cited by 28
Beilliard, Y., Paquette, F., Brousseau, F., Ecoffey, S., Alibart, F., & Drouin, D. (2020) · AIP Advances · doi:10.1063/1.5140994 · Cited by 28
Self-citationShock waves and commutation speed of memristors
Tang, S. H., Tesler, F., Gomez Marlasca, F., Lévy, P., Dobrosavljević, V., & Rozenberg, M. J. (2016) · Conicet · Cited by 28
Lin, J., & Yuan, J. S. (2019) · Neurocomputing · doi:10.1016/j.neucom.2019.09.082 · Cited by 27
Almost sure exponential synchronization of drive-response stochastic memristive neural networks
Chen, S., Feng, J., Wang, J., & Zhao, Y. (2020) · Applied Mathematics and Computation · doi:10.1016/j.amc.2020.125360 · Cited by 27
Nath, S. K., Sun, X., Nandi, S. K., Chen, X., Wang, Z., Das, S. K., Lei, W., Faraone, L., Rickard, W. D. A., & Elliman, R. G. (2023) · Advanced Functional Materials · doi:10.1002/adfm.202306428 · Cited by 27
Ex-situ training of dense memristor crossbar for neuromorphic applications
Hasan, R., Yakopcic, C., & Taha, T. M. (2015) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1109/nanoarch.2015.7180590 · Cited by 28
Bichler, O., Roclin, D., Gamrat, C., & Querlioz, D. (2013) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1109/nanoarch.2013.6623029 · Cited by 27
“Additionally, aggressively scaled down analog sub-threshold CMOS neurons and memristive nano-devices are plagued by device-to-device variations and intrinsic device variability to a large extend [16], [17].”
BackgroundMultiple memristor series–parallel connections with use in synaptic circuit design
Luo, L., Hu, X., Duan, S., Dong, Z., & Wang, L. (2016) · IET Circuits Devices & Systems · doi:10.1049/iet-cds.2015.0357 · Cited by 27
“Sofar,considerable attention has been paid to the study and use of single-memristor devices [7] and memristor cross-bar arrays [5, 12].”
BackgroundSpiking neuromorphic networks with metal-oxide memristors
Prezioso, M., Zhong, Y. F., Gavrilov, D. N., Merrikh‐Bayat, F., Hoskins, B. D., Adam, G. C., Likharev, K. K., & Strukov, D. B. (2016) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2016.7527199 · Cited by 27
Self-citationA VDTA-based robust electronically tunable memristor emulator circuit
Pal, I., Kumar, V., Aishwarya, N., Nayak, A., & Islam, A. (2019) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-019-01575-y · Cited by 27
Memristor Crossbar Circuit for Ternary Content‐Addressable Memory with Fine‐Tuning Operation
Youn, S., Kim, S., Kim, T., Park, J., & Kim, H. (2023) · Advanced Intelligent Systems · doi:10.1002/aisy.202200325 · Cited by 26
Jacobs-Gedrim, R. B., Agarwal, S., Knisely, K. E., Stevens, J. E., Heukelom, M. S. V., Hughart, D. R., Niroula, J., James, C. D., & Marinella, M. J. (2017) · IEEE International Conference on Rebooting Computing (ICRC) · doi:10.1109/icrc.2017.8123657 · Cited by 26
“It is possible to linearize a device with a nonlinear response and reduce or eliminate write variability by applying pulses of varying amplitudes/pulse widths depending on the present device resistance [13-16].”
BackgroundBanaGozar, A., Vadivel, K., Stuijk, S., Corporaal, H., Wong, S., Lebdeh, M. A., Yu, J., & Hamdioui, S. (2019) · International Workshop on Software and Compilers for Embedded Systems (SCOPES) · doi:10.1145/3323439.3323989 · Cited by 26
“it is in a crossbar or not, though, which are out of the scope of this paper [2, 16].”
BackgroundDifferentiable Content Addressable Memory with Memristors
Pedretti, G., Graves, C. E., Vaerenbergh, T. V., Serebryakov, S., Foltín, M., Sheng, X., Mao, R., Li, C., & Strachan, J. P. (2022) · Advanced Electronic Materials · doi:10.1002/aelm.202101198 · Cited by 30
Design and development of memristor‐based RRAM
Pal, S., Gupta, V., Ki, W., & Islam, A. (2019) · IET Circuits Devices & Systems · doi:10.1049/iet-cds.2018.5388 · Cited by 26
“This inherent capriciousness leads to alterations in the switching behaviour between different devices (device-to-device variations) and in a single device between different cycles (cycle-to-cycle variations) [30, 31].”
Background
Metadata
- Authors
- Alibart, F., Gao, L., Hoskins, B. D., & Strukov, D. B.
- Affiliations
- University of California, Santa Barbara (US)
- Venue
- Nanotechnology
- Publisher
- IOP Publishing
- Published
- 2012-01-20
- Volume
- 23
- Issue
- 7
- Pages
- 075201
- ISSN
- 0957-4484 (ISSN-L)
- 1361-6528
- OpenAlex
- W2091777687
- Cited by
- 557
- References
- 35
- Citations by year
- 2026: 9 · 2025: 26 · 2024: 21 · 2023: 37 · 2022: 37 · 2021: 45 · 2020: 56 · 2019: 73 · 2018: 58 · 2017: 43 · 2016: 47 · 2015: 39 · 2014: 27 · 2013: 22 · 2012: 16
- FWCI
- 21.27
- Type
- journal article
- Language
- en
- Open access
- bronze
- doi.org
- Locations
- Nanotechnology (publishedVersion)
- PubMed (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- arXiv (Cornell University)
- Funders
- National Science Foundation (1028336, 1121053)
- Division of Materials Research (DMR 1121053, 1121053)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Keywords
- memristors, TiO2 thin films, resistive switching, conductance tuning, variation tolerance, filamentary switching, non-volatile memory, analog computing, dot product computation, summing amplifier
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