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High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm
Open accessAbstract
Using memristive properties common for titanium dioxide thin film devices, we designed a simple write algorithm to tune device conductance at a specific bias point to 1% relative accuracy (which is roughly equivalent to seven-bit precision) within its dynamic range even in the presence of large variations in switching behavior. The high precision state is nonvolatile and the results are likely to be sustained for nanoscale memristive devices because of the inherent filamentary nature of the resistive switching. The proposed functionality of memristive devices is especially attractive for analog computing with low precision data. As one representative example we demonstrate hybrid circuitry consisting of an integrated circuit summing amplifier and two memristive devices to perform the analog multiply-and-add (dot-product) computation, which is a typical bottleneck operation in information processing.
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“To program an RRAM cell to its target conductance, we use an incremental-pulse write–verify technique42.”
From A compute-in-memory chip based on resistive random-access memory (2022) · cites this paper as [42]
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“Such multilevel behaviour has been exploited by a number of researchers 62–64 , showing repeatable state control from 5 different conductance levels (over 2 bits) to over 64 levels (6 bits) for a single memristor.”
BackgroundMemristive crossbar arrays for brain-inspired computing
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A compute-in-memory chip based on resistive random-access memory
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“After the conversion, we use close-loop tuning scheme [16]to program memristors to the desired conductance values.”
MethodPattern classification by memristive crossbar circuits using ex situ and in situ training
Alibart, F., Zamanidoost, E., & Strukov, D. B. (2013) · Nature Communications · doi:10.1038/ncomms3072 · Cited by 642
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Self-citationUltrafast Synaptic Events in a Chalcogenide Memristor
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Immunity to Device Variations in a Spiking Neural Network With Memristive Nanodevices
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BackgroundCompute-in-Memory Chips for Deep Learning: Recent Trends and Prospects
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“G(1)± and G(2)± are the device conductances in the first and second crossbar circuits, with ± superscripts denoting a specific device of a differential pair, while I± are the currents flowing into the corresponding neurons.”
BackgroundSelf-citationSemiconductor Quantum Dots for Memories and Neuromorphic Computing Systems
Lv, Z., Wang, Y., Chen, J., Wang, J., Zhou, Y., & Han, S. (2020) · Chemical Reviews · doi:10.1021/acs.chemrev.9b00730 · Cited by 369
Reliability of analog resistive switching memory for neuromorphic computing
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Neuromemristive Circuits for Edge Computing: A Review
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“The switching behavior of the memristive devices may vary, which affects the performance accuracy of many architectures [123].”
BackgroundA Carbon Nanotube Synapse with Dynamic Logic and Learning
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“The unintended change of the memristance during the weighting operation is negligible as long as the weighting signal amplitude is smaller than the thresholds [13]–[16] or the pulse is very narrow [21], [22].”
BackgroundGraphR: Accelerating Graph Processing Using ReRAM
Song, L., Zhuo, Y., Qian, X., Li, H. H., & Chen, Y. (2018) · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2018.00052 · Cited by 303
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Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training
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“The proposed memristor-based design should resolve the main obstacles of the above CMOS-based designs, and provide a compact nonvolatile [71] circuit.”
From biomaterial-based data storage to bio-inspired artificial synapse
Lv, Z., Zhou, Y., Han, S., & Roy, V. A. L. (2018) · Materials Today · doi:10.1016/j.mattod.2017.12.001 · Cited by 264
A general memristor-based partial differential equation solver
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4K-memristor analog-grade passive crossbar circuit
Kim, H., Mahmoodi, M. R., Nili, H., & Strukov, D. B. (2021) · Nature Communications · doi:10.1038/s41467-021-25455-0 · Cited by 265
“The analog properties of the memristive crossbar were tested by tuning device conductances using fine-tuning algorithm [48].”
MethodSelf-citation3-D Memristor Crossbars for Analog and Neuromorphic Computing Applications
Adam, G. C., Hoskins, B. D., Prezioso, M., Merrikh-Bayat, F., Chakrabarti, B., & Strukov, D. B. (2017) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2016.2630925 · Cited by 234
“, device conductance, with very high (<1%) precision [21].”
BackgroundMethodInfluentialSelf-citationEmerging Memristor-Based Logic Circuit Design Approaches: A Review
Vourkas, I., & Sirakoulis, G. C. (2016) · IEEE Circuits and Systems Magazine · doi:10.1109/mcas.2016.2583673 · Cited by 225
“Owing to their analog nature, memristors could be (at least theoretically) programmed to any intermediate resistive state between the two boundaries RON and ROFF [65].”
BackgroundNili, H., Adam, G. C., Hoskins, B. D., Prezioso, M., Kim, J., Mahmoodi, M. R., Bayat, F. M., Kavehei, O., & Strukov, D. B. (2018) · Nature Electronics · doi:10.1038/s41928-018-0039-7 · Cited by 227
“40 The goal of the tuning procedure is to enhance the contribution of the devices’ I–”
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Self-citationSelf-Adaptive Spike-Time-Dependent Plasticity of Metal-Oxide Memristors
Prezioso, M., Bayat, F. M., Hoskins, B. D., Likharev, K. K., & Strukov, D. B. (2016) · Scientific Reports · doi:10.1038/srep21331 · Cited by 212
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Nanoionic memristive phenomena in metal oxides: the valence change mechanism
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Synaptic plasticity functions in an organic electrochemical transistor
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Programmable CMOS/Memristor Threshold Logic
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“In order to characterize switching dynamics for Ag/a-Si/Pt devices, pulse protocol measurements are employed [24].”
MethodResultInfluentialSelf-citationMNSIM: Simulation Platform for Memristor-based Neuromorphic Computing System
Xia, L., Li, B., Tang, T., Gu, P., Chen, P.-Y., Yu, S., Cao, Y. K., Wang, Y., Xie, Y., & Yang, H. (2017) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2017.2729466 · Cited by 187
“The precision of memristor device is set at 7-bit memristor model [48], and the CMOS technology node is 45 nm.”
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“S11 and S12 and table S1) ( 41 , 46 – 49 ).”
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“It has been shown that the programming speed ( number of pulses needed to successfully program a conductance value ) in 1R cells is greatly affected by the voltage step parameter ( Alibart et al 2012 ) .”
BackgroundBinary convolutional neural network on RRAM
Tang, T., Xia, L., Li, B., Wang, Y., & Yang, H. (2017) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1109/aspdac.2017.7858419 · Cited by 179
“However, the current resistance precision of RRAM device is limited [9], and the impact of writing variation and reliability problem increases with the bit-level amounts of RRAM device [10].”
BackgroundNonvolatile Multistates Memories for High-Density Data Storage
Cao, Q., Lü, W., Wang, X. R., Guan, X., Wang, L., Yan, S., Wu, T., & Wang, X. (2020) · ACS Applied Materials & Interfaces · doi:10.1021/acsami.0c10184 · Cited by 173
A Memristive Multilayer Cellular Neural Network With Applications to Image Processing
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“Therefore, a special programming algorithm similar to the active feedback scheme [30], [31], which takes into account the aforementioned concerns, is adopted here.”
BackgroundBulk mixed ion electron conduction in amorphous gallium oxide causes memristive behaviour
Aoki, Y., Wiemann, C., Feyer, V., Kim, H., Schneider, C. M., Yoo, H., & Martin, M. (2014) · Nature Communications · doi:10.1038/ncomms4473 · Cited by 171
Multi-level control of conductive nano-filament evolution in HfO 2 ReRAM by pulse-train operations
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Emerging perovskite materials for high density data storage and artificial synapses
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“Hardware: The state-of-the-art fabrication result has shown the 6-bit [20] to 7-bit [1] ReRAM programmable resistance level.”
BackgroundStochastic resonance in a metal-oxide memristive device
Mikhaylov, A. N., Guseinov, D. V., Belov, A. I., Korolev, D. S., Shishmakova, V. A., Koryazhkina, M. N., Filatov, D. O., Gorshkov, O. N., Maldonado, D., Alonso, F., et al. (2021) · Chaos Solitons & Fractals · doi:10.1016/j.chaos.2021.110723 · Cited by 143
“Traditional approaches to increasing the stability of RS parameters include memristive device engineering by selecting the optimal stacks of oxide and electrode materials [25] and the use of multilayer structures [26,27], as well as special programming techniques [28,29].”
Hänsch, W., Raghunathan, A., Roy, K., Chakrabarti, B., Phatak, C., Wang, C., & Guha, S. (2022) · Advanced Materials · doi:10.1002/adma.202204944 · Cited by 148
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Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
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“In many reported synaptic devices [ 14, 16, 18, 24, 36 ] , multilevel states were achieved by varying the pulse amplitude [ 16, 18, 24 ] or the pulse width [ 14 ] , or by using a feedback scheme [ 36 ] that applies iterative write and read pulses to converge to a desired state, which adds signi fi…”
MethodSelf-citationResistive Memory-Based Analog Synapse: The Pursuit for Linear and Symmetric Weight Update
Woo, J., & Yu, S. (2018) · IEEE Nanotechnology Magazine · doi:10.1109/mnano.2018.2844902 · Cited by 138
“Meanwhile, a study was reported that solves a similar saturation problem from a power perspective [41]. as the conductance of the Mo/TiOx rraM was decreased, the amount of change was reduced because the effective power (calculated from )P V G2 #= produced by the identical voltage pulse became smaller.”
BackgroundInfluentialRRAM-Based Analog Approximate Computing
Li, B., Gu, P., Shan, Y., Wang, Y., Chen, Y., & Yang, H. (2015) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2015.2445741 · Cited by 135
“The RESET process is usually used to achieve multiple resistance states [20].”
MethodNeuromorphic Computing Based on Emerging Memory Technologies
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Self-citationMaking Memristive Neural Network Accelerators Reliable
Feinberg, B., Wang, S., & İpek, E. (2018) · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2018.00015 · Cited by 134
“propose a simple, widely used scheme for accurate memristor programming; the key idea is to successively apply a series of short pulses to converge slowly on the target resistance [37].”
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Continuous Electrical Tuning of the Chemical Composition of TaOx-Based Memristors
Miao, F., Yi, W., Goldfarb, I., Yang, J. J., Zhang, M.-X., Pickett, M. D., Strachan, J. P., Medeiros‐Ribeiro, G., & Williams, R. S. (2012) · ACS Nano · doi:10.1021/nn2044577 · Cited by 127
Memristor crossbar deep network implementation based on a Convolutional neural network
Yakopcic, C., Alom, M. Z., & Taha, T. M. (2016) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2016.7727302 · Cited by 132
Advances in Memristor-Based Neural Networks
Xu, W., Wang, J., & Yan, X. (2021) · Frontiers in Nanotechnology · doi:10.3389/fnano.2021.645995 · Cited by 132
“For the system-design level, device deviation can be reduced by protocols, such as closed loop peripheral circuit with a write-verify function (Alibart et al., 2012).”
BackgroundReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration
Long, Y., Na, T., & Mukhopadhyay, S. (2018) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2018.2819190 · Cited by 125
“longer time and consumes more energy than reading [3], [40].”
BackgroundXcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays
Agrawal, A., Jaiswal, A., Roy, D., Han, B., Srinivasan, G., Ankit, A., & Roy, K. (2019) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2019.2907488 · Cited by 123
“These include, the limited endurance of memristive devices, the multi-cycle write-verify programming scheme [23] and the drift in programmed resistance state with aging [24].”
BackgroundMultilayer Metal‐Oxide Memristive Device with Stabilized Resistive Switching
Mikhaylov, A. N., Belov, A. I., Korolev, D. S., Antonov, I. N., Kotomina, V. E., Kotina, A., Gryaznov, E. G., Шарапов, А. Н., Koryazhkina, M. N., Kryukov, R. N., et al. (2019) · Advanced Materials Technologies · doi:10.1002/admt.201900607 · Cited by 118
Enabling Scientific Computing on Memristive Accelerators
Feinberg, B., Vengalam, U. K. R., Whitehair, N., Wang, S., & İpek, E. (2018) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1109/isca.2018.00039 · Cited by 112
“The results show virtually no sensitivity to programming error for single-bit cells until the programming error reaches 5%, well within the achievable programming precision reported in the literature [58].”
BackgroundWijesinghe, P., Ankit, A., Sengupta, A., & Roy, K. (2018) · IEEE Transactions on Emerging Topics in Computational Intelligence · doi:10.1109/tetci.2018.2829924 · Cited by 113
“order to account for this, high precision write mechanisms must be incorporated.A feedback write scheme would be appropriate to make sure that the proper value has been transferred to the memristors [36], [49]. The work in [36] experimentally shows the possibility to tune the memristive device within 1% accuracy degra…”
BackgroundMethodResistive random-access memory based on ratioed memristors
Lastras-Montaño, M. Á., & Cheng, K.-T. T. (2018) · Nature Electronics · doi:10.1038/s41928-018-0115-z · Cited by 112
Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices
Linn, E., Siemon, A., Waser, R. M., & Menzel, S. (2014) · RWTH Publications (RWTH Aachen) · Cited by 108
Mahmoodi, M. R., Prezioso, M., & Strukov, D. B. (2019) · Nature Communications · doi:10.1038/s41467-019-13103-7 · Cited by 102
Self-citationEfficient training algorithms for neural networks based on memristive crossbar circuits
Kataeva, I., Merrikh-Bayat, F., Zamanidoost, E., & Strukov, D. B. (2015) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2015.7280785 · Cited by 103
Self-citationElectrochemical Ionic Synapses: Progress and Perspectives
Huang, M., Schwacke, M., Onen, M., del Alamo, J. A., Li, J., & Yildiz, B. (2022) · Advanced Materials · doi:10.1002/adma.202205169 · Cited by 110
Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices
Linn, E., Siemon, A., Waser, R. M., & Menzel, S. (2014) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2014.2332261 · Cited by 117
Extremely parallel memristor crossbar architecture for convolutional neural network implementation
Yakopcic, C., Alom, M. Z., & Taha, T. M. (2017) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2017.7966055 · Cited by 99
Programming Protocol Optimization for Analog Weight Tuning in Resistive Memories
Gao, L., Chen, P.-Y., & Yu, S. (2015) · IEEE Electron Device Letters · doi:10.1109/led.2015.2481819 · Cited by 101
“[7] proposed an adaptable variation tolerant algorithm to tune TiOx based resistive devices to an intermediate state by varying pulse widths and amplitudes.”
BackgroundSelf-citationXia, L., Tang, T., Huangfu, W., Cheng, M., Yin, X., Li, B., Wang, Y., & Yang, H. (2016) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1145/2897937.2898101 · Cited by 100
“However, the state-of-the-art RRAM devices can only support 4 to 6 bit of resistance levels [13], which means we need multiple crossbars to store a part of bits of weight in each crossbar [14] and merge the results together, as shown in Fig.”
ResultIn-Memory Computing with Resistive Memory Circuits: Status and Outlook
Pedretti, G., & Ielmini, D. (2021) · Electronics · doi:10.3390/electronics10091063 · Cited by 103
“Figure 8 summarizes the main programming methodologies for IMC [51], including multilevel (a) [43,61], binary (b) [62], unary (c) [63], multilevel with redundancy (d) [64] and slicing (e) [23].”
BackgroundStromatias, E., Neil, D., Pfeiffer, M., Galluppi, F., Furber, S. B., & Liu, S. (2015) · Frontiers in Neuroscience · doi:10.3389/fnins.2015.00222 · Cited by 101
“The influence of fabrication variance is also a concern for circuits that use memristive technology (Alibart et al., 2012), where the coefficient of variation (CV) of the devices can exceed 40% in resistive values for academic technologies.”
BackgroundModeling affections with memristor-based associative memory neural networks
Hu, X., Duan, S., Chen, G., & Chen, L. (2016) · Neurocomputing · doi:10.1016/j.neucom.2016.10.028 · Cited by 92
“experimentally demonstrated pattern classification of a single-layer memristor crossbar array based perceptron network [12] with a high-precision state tuning algorithm for memristive devices [22].”
BackgroundInterfacial versus filamentary resistive switching in TiO2 and HfO2 devices
Sassine, G., Barbera, S. L., Najjari, N., Minvielle, M., Dubourdieu, C., & Alibart, F. (2016) · Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena · doi:10.1116/1.4940129 · Cited by 91
Self-citationBellanthudawa, B. K. A., Nawalage, N. M. S. K., Handapangoda, H. M. A. K., Suvendran, S., Wijayasenarathne, K. A. S. H., Rathnasuriya, M. L. D., Wickramasinghe, P. G. M. U., Aberathna, A. A. A. U., Tennakoon, A., & Perera, I. J. J. U. N. (2023) · Nanotechnology for Environmental Engineering · doi:10.1007/s41204-023-00344-7 · Cited by 99
AgInSbTe memristor with gradual resistance tuning
Zhang, J. J., Sun, H., Li, Y., Wang, Q., Xu, X. H., & Miao, X. (2013) · Applied Physics Letters · doi:10.1063/1.4804983 · Cited by 88
Chou, T., Tang, W., Botimer, J., & Zhang, Z. (2019) · IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1145/3352460.3358328 · Cited by 92
“…steps below for every input bit vector: (1) Convert the BL outputs of MAC RRAM to analog voltages using TIAs; (2) Align the voltages as inputs to buffer RRAMs to store the analog partial sums; Since the MAC RRAM’s BL resolution is 6 bits, we propose to use 6-bit MLC RRAM [1] for the buffer RRAMs.”
MethodMemristors for Hardware Security Applications
Pang, Y., Gao, B., Lin, B., Qian, H., & Wu, H. (2019) · Advanced Electronic Materials · doi:10.1002/aelm.201800872 · Cited by 89
An associative memory circuit based on physical memristors
Guo, M., Zhu, Y., Liu, R.-Y., Zhao, K.-X., & Dou, G. (2021) · Neurocomputing · doi:10.1016/j.neucom.2021.11.034 · Cited by 68
Boolean Logic Operations and Computing Circuits Based on Memristors
Papandroulidakis, G., Vourkas, I., Vasileiadis, N., & Sirakoulis, G. C. (2014) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2014.2357351 · Cited by 84
“ration and, thus, is strongly dependent on device variations [8].”
BackgroundSchmitt, R., Kubicek, M., Sediva, E., Trassin, M., Weber, M. C., Rossi, A. M., Hutter, H., Kreisel, J., Fiebig, M., & Rupp, J. L. M. (2018) · Advanced Functional Materials · doi:10.1002/adfm.201804782 · Cited by 83
Uniting Gradual and Abrupt set Processes in Resistive Switching Oxides
Fleck, K., Torre, C. L., Aslam, N., Hoffmann‐Eifert, S., Böttger, U., & Menzel, S. (2016) · Physical Review Applied · doi:10.1103/physrevapplied.6.064015 · Cited by 81
Emerging memory technologies for neuromorphic computing
Kim, C.-H., Lim, S., Woo, S. Y., Kang, W.-M., Seo, Y.-T., Lee, S., Lee, S., Kwon, D., Oh, S., Noh, Y., et al. (2018) · Nanotechnology · doi:10.1088/1361-6528/aae975 · Cited by 83
Ismail, M., Rasheed, M., Mahata, C., Kang, M., & Kim, S. (2023) · Nano Convergence · doi:10.1186/s40580-023-00380-8 · Cited by 80
Novel charm of 2D materials engineering in memristor: when electronics encounter layered morphology
Batool, S. A., Idrees, M., Zhang, S., Han, S., & Zhou, Y. (2022) · Nanoscale Horizons · doi:10.1039/d2nh00031h · Cited by 79
Khot, A. C., Dongale, T. D., Nirmal, K. A., Sung, J. H., Lee, H. J., Nikam, R. D., & Kim, T. G. (2022) · ACS Applied Materials & Interfaces · doi:10.1021/acsami.1c23268 · Cited by 78
Yttria-stabilized zirconia cross-point memristive devices for neuromorphic applications
Emelyanov, A. V., Nikiruy, K. E., Demin, V. A., Rylkov, V. V., Belov, A. I., Korolev, D. S., Gryaznov, E. G., Павлов, Д. А., Gorshkov, O. N., Mikhaylov, A. N., et al. (2019) · Microelectronic Engineering · doi:10.1016/j.mee.2019.110988 · Cited by 75
Applications and Techniques for Fast Machine Learning in Science
Deiana, A. M., Tran, N. V., Agar, J., Blott, M., Guglielmo, G. D., Duarte, J. M., Harris, P. C., Hauck, S., Liu, M., Neubauer, M. S., et al. (2022) · Frontiers in Big Data · doi:10.3389/fdata.2022.787421 · Cited by 104
Self-citationTemperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells
Guo, X., Bayat, F. M., Prezioso, M., Chen, Y., Nguyen, B. Q., Do, N., & Strukov, D. B. (2017) · Custom Integrated Circuits Conference · doi:10.1109/cicc.2017.7993628 · Cited by 77
“After each tuning pulse, the external control circuitry read out the cell output current at standard bias conditions, and made a decision about the next pulse’s destination and amplitude, until the read-out current has reached the target value with the 5% precision [9].”
MethodSelf-citationLiu, X., Mao, M., Liu, B., Li, B., Wang, Y., Jiang, H., Barnell, M. D., Wu, Q., Yang, J. J., Li, H. H., et al. (2016) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2016.2529279 · Cited by 72
“mechanism [27].”
Metadata
- Authors
- Alibart, F., Gao, L., Hoskins, B. D., & Strukov, D. B.
- Affiliations
- University of California, Santa Barbara (US)
- Venue
- Nanotechnology
- Publisher
- IOP Publishing
- Published
- 2012-01-20
- Volume
- 23
- Issue
- 7
- Pages
- 075201
- ISSN
- 0957-4484 (ISSN-L)
- 1361-6528
- OpenAlex
- W2091777687
- Cited by
- 557
- References
- 35
- Citations by year
- 2026: 9 · 2025: 26 · 2024: 21 · 2023: 37 · 2022: 37 · 2021: 45 · 2020: 56 · 2019: 73 · 2018: 58 · 2017: 43 · 2016: 47 · 2015: 39 · 2014: 27 · 2013: 22 · 2012: 16
- FWCI
- 21.27
- Type
- journal article
- Language
- en
- Open access
- bronze
- doi.org
- Locations
- Nanotechnology (publishedVersion)
- PubMed (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- arXiv (Cornell University)
- Funders
- National Science Foundation (1028336, 1121053)
- Division of Materials Research (DMR 1121053, 1121053)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Keywords
- memristors, TiO2 thin films, resistive switching, conductance tuning, variation tolerance, filamentary switching, non-volatile memory, analog computing, dot product computation, summing amplifier
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