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High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm
Open accessAbstract
Using memristive properties common for titanium dioxide thin film devices, we designed a simple write algorithm to tune device conductance at a specific bias point to 1% relative accuracy (which is roughly equivalent to seven-bit precision) within its dynamic range even in the presence of large variations in switching behavior. The high precision state is nonvolatile and the results are likely to be sustained for nanoscale memristive devices because of the inherent filamentary nature of the resistive switching. The proposed functionality of memristive devices is especially attractive for analog computing with low precision data. As one representative example we demonstrate hybrid circuitry consisting of an integrated circuit summing amplifier and two memristive devices to perform the analog multiply-and-add (dot-product) computation, which is a typical bottleneck operation in information processing.
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“To program an RRAM cell to its target conductance, we use an incremental-pulse write–verify technique42.”
From A compute-in-memory chip based on resistive random-access memory (2022) · cites this paper as [42]
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Sorted by citations
Items 301–400 of 557
Toward large-scale access-transistor-free memristive crossbars
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“Section V concludes the paper.”
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Energy control paradigm for compliance-free reliable operation of RRAM
Shrestha, P. R., Nminibapiel, D., Kim, J., Campbell, J. P., Cheung, K. P., Deora, S., Bersuker, G. I., & Baumgart, H. (2014) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps.2014.6861164 · Cited by 11
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BackgroundMethodMemristor crossbar based implementation of a multilayer perceptron
Yakopcic, C., & Taha, T. M. (2017) · IEEE National Aerospace and Electronics Conference (NAECON) · doi:10.1109/naecon.2017.8268742 · Cited by 11
A Practical Highly Paralleled ReRAM-Based DNN Accelerator by Reusing Weight Pattern Repetitions
Zhang, Y., Jia, Z., Du, H., Xue, R., Shen, Z., & Shao, Z. (2021) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2021.3071116 · Cited by 11
Memristor-Based Cryogenic Programmable DC Sources for Scalable In Situ Quantum-Dot Control
Mouny, P.-A., Beilliard, Y., Graveline, S., Roux, M.-A., Mesoudy, A. E., Dawant, R., Gliech, P., Ecoffey, S., Alibart, F., Pioro-Ladrière, M., et al. (2023) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2023.3244133 · Cited by 11
Self-citation3D-DPE: A 3D high-bandwidth dot-product engine for high-performance neuromorphic computing
Lastras-Montaño, M. Á., Chakrabarti, B., Strukov, D. B., & Cheng, K.-T. T. (2017) · Design, Automation, and Test in Europe · doi:10.23919/date.2017.7927183 · Cited by 11
“We employed the programming algorithm proposed in [7] to program the weights of the RRAM cells.”
BackgroundMethodSelf-citationTowards memristor-based approximate accelerator: application to complex-valued FIR filter bank
Nourazar, M., Rashtchi, V., Merrikh‐Bayat, F., & Azarpeyvand, A. (2018) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-018-1209-2 · Cited by 11
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Accelerating AI Applications using Analog In-Memory Computing
Channamadhavuni, S., Thijssen, S., Jha, S. K., & Ewetz, R. (2021) · ACM Great Lakes Symposium on VLSI (GLSVLSI) · doi:10.1145/3453688.3461746 · Cited by 11
“, the resistive devices can be programmed to 2 distinguishable conductance states [3, 15].”
BackgroundLee, J., Kim, J.-D., Baek, Y.-J., Choi, Y. J., Kang, C. J., Lee, H. H., & Yoon, T. (2014) · Applied Physics Letters · doi:10.1063/1.4868015 · Cited by 11
Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant Training
Pham, K. V., Nguyen, T. V., & Min, K. (2019) · Micromachines · doi:10.3390/mi10040245 · Cited by 11
“In addition, we can observe variation-related defects, where each memristor can have different LRS and HRS values [10].”
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Wan, W., Kubendran, R. C., Schaefer, C., Eryilmaz, S. B., Zhang, W., Wu, D., Deiss, S. R., Raina, P., Qian, H., Gao, B., et al. (2021) · arXiv (Cornell University) · doi:10.48550/arxiv.2108.07879 · Cited by 11
“To program an RRAM cell to its target conductance, we use an incremental-pulse write-verify technique 40 .”
MethodMeng, Z., Qian, W., Zhao, Y., Sun, Y., Yang, R., & Jiang, L. (2021) · 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) · doi:10.23919/date51398.2021.9474179 · Cited by 10
“Although the repeated programming method is a potential solution [5], [6], it needs to program the device many times, which shortens the device lifetime.”
MethodDeng, Z., Zhang, L., Franklin, D. M., & Chong, F. T. (2015) · International Symposium on Memory Systems (MEMSYS) · doi:10.1145/2818950.2818981 · Cited by 10
“Alibart et al. [1] showed that a single resistive memory cell can be used to store up to seven bits of data.”
BackgroundDesign of Tunable Analog Filters Using Memristive Crossbars
Korkmaz, A., He, C., Katehi, L. P. B., Williams, R. S., & Palermo, S. M. (2021) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas51556.2021.9401275 · Cited by 10
Efficient Hybrid Training Method for Neuromorphic Hardware Using Analog Nonvolatile Memory
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“After that, the trained weights are transferred to the conductance of analog nonvolatile memory cells in hardware [41], [45], [46].”
An Aging Resilient Neural Network Architecture
Mozaffari, S. N., Gnawali, K. P., & Tragoudas, S. (2018) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1145/3232195.3232208 · Cited by 10
Quaternary synapses network for memristor-based spiking convolutional neural networks
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“In the simulation process, we use device resistance at di ff erent levels and randomly generate 1% – 20% errors in memristor programming [31].”
MethodChoi, H.-S., Lee, J., Kim, B., Lee, J., Park, B., Kim, Y., & Hong, S. W. (2022) · Nanotechnology · doi:10.1088/1361-6528/ac805d · Cited by 10
Lin, Y., Tang, J.-S., Gao, B., Qin, Q., Zhang, Q., Qian, H., & Wu, H.-Q. (2023) · IEEE Transactions on Circuits and Systems - II - Express Briefs · doi:10.1109/tcsii.2022.3224470 · Cited by 10
“To address the issue of the transfer error, Alibart et al. [13] proposed a simple, widely used closed-loop feedback scheme to modulate the RRAM conductance.”
Volatile memristive devices as short-term memory in a neuromorphic learning architecture
Bürger, J., & Teuscher, C. (2014) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1145/2770287.2770313 · Cited by 10
Overview of Circuits, Systems, and Applications of Spintronics
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Bennett, C. H., Parmar, V., Calvet, L. E., Klein, J., Suri, M., Marinella, M. J., & Querlioz, D. (2019) · IEEE Access · doi:10.1109/access.2019.2920076 · Cited by 11
“Several varieties of industrial and academic devices including phase change memories [28]–[30], filamentarymigrating oxide devices [31], filamentary devices exploiting polymeric redox mechanisms [8], [32], and ferroelectric tunnel junction synapses [33], meet these criteria and may subsequently be integrated into dens…”
BackgroundMethodGomez, J. T., Vourkas, I., Hoffman, A. C. A., Rodriguez, R., Martin-Martinez, J., Nafria, M., & Rubio, A. (2019) · Solid-State Electronics · doi:10.1016/j.sse.2019.107748 · Cited by 10
“More specifically, a precise RESET (implementing the tuning algorithm suggested in [28]) took place before each SET experiment.”
MethodResistive Crossbar-Aware Neural Network Design and Optimization
Hanif, M. A., Manglik, A., & Shafique, M. (2020) · IEEE Access · doi:10.1109/access.2020.3045071 · Cited by 11
“5) These recommendations are orthogonal to hardware innovations and software optimizations presented in prior works [92]–[94], which ensures future relevance of these ideas and algorithms.”
Effect of ZnS and PbS shell on mem-behavior of CdS quantum dots
Das, H., Xu, Q., & Datta, P. (2021) · Journal of Materials Science Materials in Electronics · doi:10.1007/s10854-021-05415-6 · Cited by 11
Variation-Tolerant Capacitive Array for Binarized Neural Network
Kim, H., Woo, S. Y., Lee, S., Seo, Y.-T., Park, B., & Lee, J. (2022) · IEEE Electron Device Letters · doi:10.1109/led.2022.3143140 · Cited by 10
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On the Reliability of Computing-in-Memory Accelerators for Deep Neural Networks
Yan, Z., Hu, X. S., & Shi, Y. (2022) · Springer series in reliability engineering · doi:10.1007/978-3-031-02063-6_9 · Cited by 12
Exploring the voltage divider approach for accurate memristor state tuning
Vourkas, I., Gomez, J. T., Hoffman, A. C. A., Vasileiadis, N., Sirakoulis, G. C., & Rubio, A. (2017) · IEEE Latin American Symposium on Circuits and Systems (LASCAS) · doi:10.1109/lascas.2017.7948043 · Cited by 10
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Self-citationPhysics-Technological Fabrication of Memresistors for Micro- and Nanoelectronics
Belov, A. N., Perevalov, A. A., & Shevyakov, V. I. (2017) · Proceedings of Universities ELECTRONICS · doi:10.24151/1561-5405-2017-22-4-305-321 · Cited by 9
Design of CNFET based power- and variability-aware nonvolatile RRAM cell
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“The last step is to program the state variables to the hardware using accurate closed-loop tuning [1], [21].”
BackgroundMethodCycle-to-cycle Variation Enabled Energy Efficient Privacy Preserving Technology in ANN
Fu, J., Liao, Z., & Wang, J. (2020) · IEEE International System-on-Chip Conference (SOCC) · doi:10.1109/socc49529.2020.9524794 · Cited by 9
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A Coordinated Model Pruning and Mapping Framework for RRAM-Based DNN Accelerators
Qu, S., Li, B., Zhao, S., Zhang, L., & Wang, Y. (2022) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2022.3221906 · Cited by 9
“The multiplication result, [ − 1, 7] vector from RRAM crossbars justifies that our mapping method can get the correct output.”
MethodYue, J., Liu, Y., Su, F., Li, S., Yuan, Z., Wang, Z., Sun, W., Li, X., & Yang, H. (2019) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1145/3287624.3287635 · Cited by 9
“A ReRAM cell with low/high resistance can represent logic ‘0’/‘1’, and a ReRAM cell with multi-level resistance state can represent multi-bit data [1, 20].”
BackgroundA bridge technique for memristor state programming
Tarkhan, M., Maymandi‐Nejad, M., Klidbary, S. H., & Shouraki, S. B. (2019) · International Journal of Electronics · doi:10.1080/00207217.2019.1692371 · Cited by 9
“, 2011) 350nm 40μs 3-bit _ (Alibart et al., 2012) Discrete 10ms 8-bit _ (Elshamy et al.”
Cao, T., Goh, W. L., & Gao, Y. (2020) · Intelligent Autonomous Systems · doi:10.1109/icoias49312.2020.9081857 · Cited by 10
Exploring Image Selection for Self-Testing in Neural Network Accelerators
Meng, F., & Yang, C. (2022) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi54635.2022.00076 · Cited by 8
“For instance, programming of an RRAM cell does not set the conductance to the expected value, but rather on a normal distribution within the objective range [13].”
BackgroundPRAP-PIM: A weight pattern reusing aware pruning method for ReRAM-based PIM DNN accelerators
Shen, Z., Wu, J., Jiang, X., Zhang, Y., Ju, L., & Jia, Z. (2023) · High-Confidence Computing · doi:10.1016/j.hcc.2023.100123 · Cited by 8
A Hybrid Weight Quantization Strategy for Memristive Neural Networks
Shen, S., Duan, S., & Wang, L. (2023) · Neurocomputing · doi:10.1016/j.neucom.2023.126778 · Cited by 8
Highly-uniform multi-layer ReRAM crossbar circuits
Adam, G. C., Hoskins, B. D., Prezioso, M., Bayat, F. M., Chakrabarti, B., & Strukov, D. B. (2016) · European Solid-State Device Research Conference · doi:10.1109/essderc.2016.7599679 · Cited by 8
“Each device was first tuned to a high resistance state of 200 kΩ, then voltage pulses of gradually increasing positive amplitude were apply to set the device to 70 kΩ [19].”
MethodSelf-citationMemristor-based approximate matrix multiplier
Nourazar, M., Rashtchi, V., Azarpeyvand, A., & Merrikh‐Bayat, F. (2017) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-017-1029-9 · Cited by 8
“Recent research shows that the memristor’s fine tuning can be precisely programmed to realize 7-bit precision [36, 37].”
BackgroundChen, X., Jiang, J., Zhu, J., & Tsui, C.-Y. (2018) · doi:10.5555/3201607.3201633 · Cited by 8
Analysis and Design of Memristor Crossbar Based Neuromorphic Intrusion Detection Hardware
Yakopcic, C., & Taha, M. T. (2018) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2018.8489252 · Cited by 8
Liu, H., Han, J., & Zhang, Y. (2019) · IEEE Computer Architecture Letters · doi:10.1109/lca.2019.2908374 · Cited by 8
“By default the IO precision is 8-bit and the weight precision is 256-level [21]; the input of DAC is a series of 1-bit signals, 32 crossbar-columns share an ADC and the crossbar size is 128 128.”
Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks
Majumdar, A., Bocquet, M., Hirtzlin, T., Laborieux, A., Klein, J., Nowak, E., Vianello, E., Portal, J., & Querlioz, D. (2021) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2021.3108479 · Cited by 8
“Although studies about low voltage switching [16], device models [17], and noise [18], [19] have been carried out in the past, a comprehensive study integrating all these aspects have not been done.”
BackgroundEnabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network
Li, X., Wu, B., Sun, G., Zhang, Z., Yuan, Z., Wang, R., Huang, R., Niu, D., Zheng, H., Lu, Z., et al. (2022) · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · doi:10.1109/hpca53966.2022.00080 · Cited by 8
Spectral Ranking in Complex Networks Using Memristor Crossbars
Korkmaz, A., Zoppo, G., Marrone, F., Yi, S., Williams, R. S., Corinto, F., & Palermo, S. M. (2023) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2023.3237836 · Cited by 8
“The details on the memristors and device programming can be found in our previous and other relevant works [4], [14], [32], [33].”
BackgroundA Low-Latency DNN Accelerator Enabled by DFT-Based Convolution Execution Within Crossbar Arrays
Veluri, H., Chand, U., Chen, C.-K., & Thean, A. (2023) · IEEE Transactions on Neural Networks and Learning Systems · doi:10.1109/tnnls.2023.3327122 · Cited by 9
“The high-precision device-tuning approaches required to tackle RRAM variability issues [15], [16], in conjunction with the columnwise programming of the crossbar array, result in a long device tuning time during neural network training.”
A Designer's Rationale for Nanoelectronic Hardware Security Primitives
Rose, G. S., Uddin, M., & Majumder, M. B. (2016) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi.2016.114 · Cited by 8
“neuromorphic computing system [18], [19].”
Generalized reconfigurable memristive dynamical system (MDS) for neuromorphic applications
Bavandpour, M., Soleimani, H., Linares-Barranco, B., Abbott, D., & Chua, L. O. (2015) · Frontiers in Neuroscience · doi:10.3389/fnins.2015.00409 · Cited by 8
“In the context of analog and mixed circuit applications, recent advances in memristive devices and their integration with CMOS enable efficient implementations of nanoscale analog-grade resistive elements that can be fine-tuned after fabrication (Alibart et al., 2012).”
BackgroundApplications of solid-state memristors in tunable filters
Wizenberg, R., Khiat, A., Berdan, R., Papavassiliou, C., & Prodromakis, T. (2014) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2014.6865623 · Cited by 8
Conductance variability in RRAM and its implications at the neural network level
Aziza, H., Fieback, M., Hamdioui, S., Xun, H., & Taouil, M. (2025) · Microelectronics Reliability · doi:10.1016/j.microrel.2025.115594 · Cited by 7
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“In practical implementations, Alibart et al. [147] and Kim et al. [148] have employed multiple write-verify cycles combined with incremental or decremental pulse amplitude sequences to decompose the conductance tuning process into finely controlled steps (Figure 9(a)).”
Men, M., Deng, Z., Zhao, Z., Liu, L., Cui, Y., Jin, S., Xie, Y., Jiang, X., Ren, W., Hong, J., et al. (2026) · Nature Communications · doi:10.1038/s41467-026-68853-y · Cited by 7
“Moreover, the symmetry of photo-responsivity weight can be improved by a programming algorithm to increase the photoresponsivity accuracy 31 .”
Thermal Modeling of Resistive Switching Devices
Ramu, A. T., & Strukov, D. B. (2013) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2013.2256138 · Cited by 7
“In addition, the ionic nature of the memory effect typically ensures excellent scaling prospects [10], which can be often combined with multistate or analog memory capabilities [11].”
BackgroundSelf-citationFayyazi, A., Kundu, S., Nazarian, S., Beerel, P. A., & Pedram, M. (2019) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi.2019.00090 · Cited by 7
“5V, respectively, and to ensure 99% write accuracy in presence of device variation and stochastic write we used the scheme of [28] (the write operation is performed memristor-by-memristor).”
MethodResonant activation of resistive switching in ZrO2(Y) films
Ryabova, M. A., Filatov, D. O., Коряжкина, М. Н., Александрович, А. Д., Antonov, I. N., Gorshkov, O. N., Kharcherva, A. A., & Dubkov, A. A. (2021) · Journal of Physics Conference Series · doi:10.1088/1742-6596/1851/1/012003 · Cited by 7
ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption
Lin, N., Chen, X., Xia, C., Ye, J., & Li, X. (2021) · Proceedings - Asian Test Symposium/Proceedings · doi:10.1109/ats52891.2021.00013 · Cited by 7
Rescuing ReRAM-based Neural Computing Systems from Device Variation
Huang, C., Xu, N., Zeng, J., Wang, W., Hu, Y., Fang, L., Ma, D., & Chen, Y.-T. (2022) · ACM Transactions on Design Automation of Electronic Systems · doi:10.1145/3533706 · Cited by 7
“Several methods have been recently proposed to conquer device variation in RCA [2, 5, 24, 26, 29].”
MethodDamascene versus subtractive line CMP process for resistive memory crossbars BEOL integration
Dawant, R., Gaudreau, M., Roy, M.-A., Mouny, P.-A., Valdenaire, M., Gliech, P., Arias‐Zapata, J., Zegaoui, M., Alibart, F., Drouin, D., et al. (2024) · Micro and Nano Engineering · doi:10.1016/j.mne.2024.100251 · Cited by 7
Self-citationWoods, W., Bürger, J., & Teuscher, C. (2014) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1145/2770287.2770292 · Cited by 7
“In [5] a tuning algorithm was able to adjust memristive states to a roughly 7 bit resolution.”
InfluentialProgramming protocol optimization for analog weight tuning in resistive memories
Gao, L., & Yu, S. (2015) · Conference digest · doi:10.1109/drc.2015.7175619 · Cited by 7
Self-citationProspects for Analog Circuits in Deep Networks
Liu, S., Strachan, J. P., & Basu, A. (2021) · Springer eBooks · doi:10.1007/978-3-030-91741-8_4 · Cited by 9
The Impact of Device Uniformity on Functionality of Analog Passively-Integrated Memristive Circuits
Fahimi, Z., Mahmoodi, M. R., Klachko, M., Nili, H., & Strukov, D. B. (2021) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2021.3097282 · Cited by 7
“To clarify this, consider the practical V/2 approach [7], [9] of tuning memristive crossbars (Fig.”
BackgroundMethodInfluentialSelf-citationFast and Low-Cost Mitigation of ReRAM Variability for Deep Learning Applications
Lee, S., Fouda, M. E., Lee, J., Eltawil, A. M., & Kurdahi, F. J. (2021) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd53106.2021.00051 · Cited by 7
Parasitic-Aware Modelling for Neural Networks Implemented with Memristor Crossbar Array
Cao, T., Liu, C., Gao, Y., & Goh, W. L. (2021) · IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) · doi:10.1109/mcsoc51149.2021.00025 · Cited by 9
Rectifying Resistive Memory Devices as Dynamic Complementary Artificial Synapses
Berco, D. (2018) · Frontiers in Neuroscience · doi:10.3389/fnins.2018.00755 · Cited by 7
“, 2010) in response to successive set and reset pulses (Alibart et al., 2012; Chen et al., 2015; Wang et al., 2016) that complicate the task of designing a control state machine and sensing circuitry.”
BackgroundMethodLow Power Artificial Neural Network ArchitecturePreprint
Gnawali, K. P., Mozaffari, S. N., & Tragoudas, S. (2019) · arXiv (Cornell University) · doi:10.48550/arxiv.1904.02183 · Cited by 7
“Thus, 𝑀 , and 𝑀 , were implemented with a 5-bit memristive multi-level cell [27-29].”
BackgroundMethodGonugondla, S. K., Patil, A. D., & Shanbhag, N. R. (2020) · IEEE/ACM ICCAD · doi:10.1145/3400302.3415642 · Cited by 6
“Furthermore, SWIPE programs each BC pair only once, making it significantly (5×-to-10×) more efficient compared to the standard program-verify techniques [2, 5, 7].”
MethodYoun, S., Hwang, H., & Kim, H. (2025) · Advanced Intelligent Systems · doi:10.1002/aisy.202500817 · Cited by 6
Towards scalable cryogenic quantum dot biasing using memristor-based DC sources
Mouny, P.-A., Dawant, R., Dufour, P., Valdenaire, M., Ecoffey, S., Pioro-Ladrière, M., Beilliard, Y., & Drouin, D. (2024) · Cryogenics · doi:10.1016/j.cryogenics.2024.103910 · Cited by 6
A Data-Driven Stochastic Memristor Model for Integrated Circuit Simulation
Xie, L., Shen, J., Feng, P., Mifsud, A., Malik, A., Nassibi, A., Manatchinapisit, V., & Papavassiliou, C. (2024) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2024.3485584 · Cited by 6
“The pulsing scheme that initializes the resistance at a consistently low level and then programs it to multiple higher states has been widely exploited in memristor characterizations and applications [15], [17], [22], [45], [46].”
Choi, S., Jang, J., Kim, M. S., Kim, N. D., Kwag, J., & Wang, G. (2022) · Advanced Science · doi:10.1002/advs.202104773 · Cited by 5
Wang, M., Huang, M., Wang, C., Sun, H., Miao, X., & Wang, X. (2023) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2023.3294352 · Cited by 6
“and 2) a write-verify technique [13], [14], [15], [16], [17] is adopted by repeatedly applying either a set or a reset-pulse and following the verification whether the conductance approaches the target value.”
MethodBio-Inspired Information Pathways
Ziegler, M., Mussenbrock, T., & Kohlstedt, H. (2023) · Springer series on bio- and neurosystems · doi:10.1007/978-3-031-36705-2 · Cited by 7
A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing
Chen, W., Gu, F.-Y., Lin, I.-C., Zhang, G. L., Li, B., & Schlichtmann, U. (2023) · doi:10.1109/iccad57390.2023.10323793 · Cited by 6
“This adjustment is made by applying a voltage to the ReRAM cell and then reading its conductance after the change, a mechanism known as program-and-verify [4].”
MethodSelf-Organization in Autonomous, Recurrent, Firing-Rate CrossNets With Quasi-Hebbian Plasticity
Walls, T. J., & Likharev, K. K. (2013) · IEEE Transactions on Neural Networks and Learning Systems · doi:10.1109/tnnls.2013.2280904 · Cited by 6
“there has been a fast progress in the fabrication of memristive crosspoint devices1 whose electric resistance may be precisely tuned to an arbitrary value (within a certain range)—see [9].”
BackgroundBennett, C. H., Lorival, J.-E., Marc, F., Cabaret, T., Jousselme, B., Derycke, V., Klein, J., & Maneux, C. (2017) · IEEE Transactions on Multi-Scale Computing Systems · doi:10.1109/tmscs.2017.2773523 · Cited by 6
Maximizing the Number of Threshold Logic Functions Using Resistive Memory
Mozaffari, S. N., & Tragoudas, S. (2018) · IEEE Transactions on Nanotechnology · doi:10.1109/tnano.2018.2822285 · Cited by 6
Berco, D., & Ang, D. S. (2019) · Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena · doi:10.1116/1.5123665 · Cited by 6
Study of the Formation Process of Memristor Structures Based on Copper Sulfide
Belov, A. N., Golishnikov, A. A., Mastinin, A. M., Perevalov, A. A., & Shevyakov, V. I. (2019) · Semiconductors · doi:10.1134/s1063782619150041 · Cited by 6
A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators
Zhang, C., & Zhou, P. (2021) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1145/3394885.3431528 · Cited by 6
“Stateof-the-art ReRAM device can achieve up to 7-bit precision for a single device [20], by iterative read-verify-write operations until the resistance converges to the desired value.”
BackgroundJeng, E. S., Chen, H. X., Chiang, Y.-L., Chang, J.-P., & Chen, J. Y. (2019) · Microelectronics Journal · doi:10.1016/j.mejo.2019.07.001 · Cited by 6
Kwon, D., Park, M., Kang, W.-M., Hwang, J., Koo, R., Bae, J., & Lee, J. (2023) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2023.3287824 · Cited by 5
“One way to address the variation problem is to adopt iterative weight tuning schemes that verify the conductance of synaptic devices is set to the target value [10], [32], [33].”
BackgroundA Monte Carlo analysis of a write method used in passive nanoelectronic crossbars
Heittmann, A., & Noll, T. G. (2012) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1145/2765491.2765509 · Cited by 5
The effect of Ti and O ion implantation on the resistive switching in Pt/TiO2−x /Pt devices
Gao, L., Hoskins, B. D., Zaynetdinov, M., Kochergin, V., & Strukov, D. B. (2015) · Applied Physics A · doi:10.1007/s00339-015-9368-9 · Cited by 5
Self-citation3D hybrid CMOS/memristor circuits: Basic principle and prospective applications
Strukov, D. B. (2012) · Conference on Optoelectronic and Microelectronic Materials and Devices (COMMAD) · doi:10.1109/commad.2012.6472340 · Cited by 5
Self-citationZhang, B., Uysal, N., Fan, D., & Ewetz, R. (2020) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1109/asp-dac47756.2020.9045101 · Cited by 5
“The computational accuracy is evaluated while accounting for that memristors only can be programmed to a limited number of distinguishable states [1], [4].”
BackgroundMethodVector multiplications using memristive devices and applications thereof
Zidan, M. A., & Lu, W. D. (2020) · Elsevier eBooks · doi:10.1016/b978-0-08-102782-0.00009-5 · Cited by 5
A Fast Precision Tuning Solution for Always-On DNN Accelerators
Wang, Y., He, Y., Cheng, L., Li, H., & Li, X. (2021) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2021.3089667 · Cited by 5
Su, P.-C., Jiang, C.-M., Wang, C., & Wang, T. (2018) · IEEE Electron Device Letters · doi:10.1109/led.2018.2868472 · Cited by 5
“[13] D. S. Jeong, H. Schroeder, U. Breuer, and R. Waser, “Characteristic electroforming behavior in Pt/TiO2/Pt resistive switching cells depending on atmosphere,” J. Appl.”
InfluentialTikhov, S. V., Belov, A. I., Korolev, D. S., Antonov, I. N., Sushkov, A. A., Павлов, Д. А., Tetelbaum, D. I., Gorshkov, O. N., & Михайлов, А. Н. (2020) · Technical Physics · doi:10.1134/s1063784220020231 · Cited by 5
Utilizing I-V non-linearity and analog state variations in ReRAM-based security primitives
Adam, G. C., Nili, H., Kim, J., Hoskins, B. D., Kavehei, O., & Strukov, D. B. (2017) · European Solid-State Device Research Conference · doi:10.1109/essderc.2017.8066595 · Cited by 5
“The devices were tuned to 1% precision using the tuning algorithm presented in [16] with 500 μS long voltage pulses of maximum amplitudes ±2.”
MethodSelf-citation
Metadata
- Authors
- Alibart, F., Gao, L., Hoskins, B. D., & Strukov, D. B.
- Affiliations
- University of California, Santa Barbara (US)
- Venue
- Nanotechnology
- Publisher
- IOP Publishing
- Published
- 2012-01-20
- Volume
- 23
- Issue
- 7
- Pages
- 075201
- ISSN
- 0957-4484 (ISSN-L)
- 1361-6528
- OpenAlex
- W2091777687
- Cited by
- 557
- References
- 35
- Citations by year
- 2026: 9 · 2025: 26 · 2024: 21 · 2023: 37 · 2022: 37 · 2021: 45 · 2020: 56 · 2019: 73 · 2018: 58 · 2017: 43 · 2016: 47 · 2015: 39 · 2014: 27 · 2013: 22 · 2012: 16
- FWCI
- 21.27
- Type
- journal article
- Language
- en
- Open access
- bronze
- doi.org
- Locations
- Nanotechnology (publishedVersion)
- PubMed (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- arXiv (Cornell University)
- Funders
- National Science Foundation (1028336, 1121053)
- Division of Materials Research (DMR 1121053, 1121053)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Keywords
- memristors, TiO2 thin films, resistive switching, conductance tuning, variation tolerance, filamentary switching, non-volatile memory, analog computing, dot product computation, summing amplifier
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