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High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm
Open accessAbstract
Using memristive properties common for titanium dioxide thin film devices, we designed a simple write algorithm to tune device conductance at a specific bias point to 1% relative accuracy (which is roughly equivalent to seven-bit precision) within its dynamic range even in the presence of large variations in switching behavior. The high precision state is nonvolatile and the results are likely to be sustained for nanoscale memristive devices because of the inherent filamentary nature of the resistive switching. The proposed functionality of memristive devices is especially attractive for analog computing with low precision data. As one representative example we demonstrate hybrid circuitry consisting of an integrated circuit summing amplifier and two memristive devices to perform the analog multiply-and-add (dot-product) computation, which is a typical bottleneck operation in information processing.
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“To program an RRAM cell to its target conductance, we use an incremental-pulse write–verify technique42.”
From A compute-in-memory chip based on resistive random-access memory (2022) · cites this paper as [42]
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Cites
Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges
Waser, R., Dittmann, R., Staikov, G., & Szot, K. (2009) · Advanced Materials · doi:10.1002/adma.200900375 · Cited by 5,080
Nanoscale Memristor Device as Synapse in Neuromorphic Systems
Jo, S. H., Chang, T., Ebong, I., Bhadviya, B. B., Mazumder, P., & Lu, W. (2010) · Nano Letters · doi:10.1021/nl904092h · Cited by 4,174
Memristive switching mechanism for metal/oxide/metal nanodevices
Yang, J. J., Pickett, M. D., Li, X., Ohlberg, D. A. A., Stewart, D. R., & Williams, R. S. (2008) · Nature Nanotechnology · doi:10.1038/nnano.2008.160 · Cited by 2,987
Resistive switching in transition metal oxides
Sawa, A. (2008) · Materials Today · doi:10.1016/s1369-7021(08)70119-6 · Cited by 2,949
Atomic structure of conducting nanofilaments in TiO2 resistive switching memory
Kwon, D.-H., Kim, K. M., Jang, J. H., Jeon, J. M., Lee, M. H., Kim, G. H., Li, X.-S., Park, G.-S., Lee, B., Han, S., et al. (2010) · Nature Nanotechnology · doi:10.1038/nnano.2009.456 · Cited by 2,092
Resistance switching memories are memristors
Chua, L. (2011) · Applied Physics A · doi:10.1007/s00339-011-6264-9 · Cited by 1,434
Reproducible switching effect in thin oxide films for memory applications
Beck, A., Bednorz, J. G., Gerber, C., Rossel, C., & Widmer, D. (2000) · Applied Physics Letters · doi:10.1063/1.126902 · Cited by 1,129 · cited 1×
“However, for all other applications, e.g., multilevel memory [Bec00, Yu11a, Cho06], configurable filters [Dri10], and analog computing circuits (see, e.g., various theoretical proposals in Refs.”
BackgroundMemory effects in complex materials and nanoscale systems
Pershin, Y. V., & Di Ventra, M. (2011) · Advances In Physics · doi:10.1080/00018732.2010.544961 · Cited by 823
Yu, S., Wu, Y., Jeyasingh, R., Kuzum, D., & Wong, H.-S. P. (2011) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2011.2147791 · Cited by 805
Switching dynamics in titanium dioxide memristive devices
Pickett, M. D., Strukov, D. B., Borghetti, J. L., Yang, J. J., Snider, G. S., Stewart, D. R., & Williams, R. S. (2009) · Journal of Applied Physics · doi:10.1063/1.3236506 · Cited by 775
Self-citation
Research works printed but not linked: 7
- Kim K M, 2011, Nanotechnology, 22
- Lee J Park J Jung S Hwang H, 2011, Proc. Int. Technology Conf. and Materials for Advanced Metallization, 1
- Papandreou N Pozidis H Pantazi A Sebastian A Breitwisch M Lam C Eleftheriou E, 2011, Proc. IEEE Int. Symp. on Circuits and Systems, 329
- Prodromakis T Toumazou C, 2010, Proc. IEEE Int. Conf. on Electronics, Circuits, and Systems, 934
- Seo K, 2011, Nanotechnology, 22
- Snider G S, 2007, Nanotechnology, 18
- Strachan J P, 2011, Nanotechnology, 22
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Items 401–500 of 557
Song, H., An, J., Son, S., Kim, Y. S., Park, J., Jeon, J. B., Kim, G., & Kim, K. M. (2020) · Advanced Intelligent Systems · doi:10.1002/aisy.202000014 · Cited by 4
Wang, T., Ran, H., Guo, J., Wang, W., Hu, X., Liao, C., Sun, B. T., Kang, Y., & Zhou, G. (2025) · Physical Chemistry Chemical Physics · doi:10.1039/d5cp02403j · Cited by 4
Zhao, X., Liu, L., Liu, Y., Gao, B., & Sun, H. (2024) · Microelectronics Journal · doi:10.1016/j.mejo.2024.106189 · Cited by 4
Difficulties and approaches in enabling learning-in-memory using crossbar arrays of memristors
Wang, W. J., Li, Y., & Wang, M. (2024) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/ad6732 · Cited by 4
“One can use increasing pulse amplitude or uniform pulse amplitude when continuous potentiation or depression pulses are needed in the loop [57].”
Experimental Demonstration of Firing Rate Neural Networks Based on Metal-Oxide Memristive Crossbars
Bayat, F. M., Prezioso, M., & Chakrabarti, B. (2017) · Springer eBooks · doi:10.1007/978-3-319-54313-0_6 · Cited by 4
Deb, S., Vatwani, T., Chattopadhyay, A., Basu, A., & Fong, X. (2018) · IEEE Transactions on Biomedical Circuits and Systems · doi:10.1109/tbcas.2018.2867038 · Cited by 4
“We implement a high-precision write algorithm [31] to tune a synaptic memristor within 2% of the desired conductance level.”
MethodImproving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory
Wang, C., Feng, D., Tong, W., Hua, Y., Liu, J., Wu, B., Zhao, W. J., Song, L., Zhang, Y., Xu, J., et al. (2020) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2020.3006188 · Cited by 4
Herranz, A. D. G., & López‐Vallejo, M. (2020) · Integration · doi:10.1016/j.vlsi.2020.07.001 · Cited by 4
Filatov, D. O., Коряжкина, М. Н., Александрович, А. Д., Antonov, I. N., Liskin, D., Ryabova, M. A., & Gorshkov, O. N. (2019) · IOP Conference Series Materials Science and Engineering · doi:10.1088/1757-899x/699/1/012012 · Cited by 4
Error Correction Scheme for Reliable RRAM-Based In-Memory Computing
Hu, Y., Cheng, K., Zhang, Z., Wang, R., Wang, Y., & Huang, R. (2021) · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · doi:10.1109/edtm50988.2021.9420944 · Cited by 4
“So it can be combined with other schemes of reducing the circuit variations (e.g., [8] [10]).”
BackgroundState-Space Modeling and Tuning of Memristors for Neuromorphic Computing Applications
Yang, M.-J., & Strachan, J. P. (2023) · International Conference on Neuromorphic Systems (ICONS) · doi:10.1145/3589737.3605966 · Cited by 4
“Figure 6 shows the simulated tuning processes, comparing two typical write-and-verify approaches, i.e., identical pulse programming (IPP) and incremental step pulse programming (ISPP) [30, 31].”
BackgroundMethodInfluentialNeural image caption generator based on crossbar array design of memristor module
Yu, Y., Yang, D., Tang, Q. J., Wang, X., Yang, N., Cheng, M., Zhong, Y., Adu, K., & Ekong, F. (2023) · Neurocomputing · doi:10.1016/j.neucom.2023.126766 · Cited by 7
The Dynamic Tunability of Memristor-Based Active Filters
Marković, I., Potrebić, M. M., & Tošić, D. V. (2023) · Micromachines · doi:10.3390/mi14112064 · Cited by 4
“…to the unpredictable This means that the memrsitor could change its memristance on the fly and that the control signal, i.e., the memristor programming signal, should be suppressed at the filter output. and challenging nature of precisely and repeatably controlling the memristor’s state [36–40].”
BackgroundOkulich, E. V., Koryazhkina, M. N., Korolev, D. S., Belov, A. I., Шенина, М. Е., Mikhaylov, A. N., Tetelbaum, D. I., Antonov, I. N., & Dudin, Y. A. (2019) · Technical Physics Letters · doi:10.1134/s1063785019070253 · Cited by 4
Review of candidate devices for neuromorphic applications
Lee, J., Woo, S. Y., Lee, S., Lim, S., Kang, W.-M., Seo, Y.-T., Lee, S., Kwon, D., Oh, S., Noh, Y., et al. (2019) · European Solid-State Device Research Conference · doi:10.1109/essderc.2019.8901694 · Cited by 5
Bioinspired neuromorphic module based on carbon nanotube/C60/polymer composite
Kim, K.-H., Tudor, A., Chen, C.-L., Lee, D., Shen, A. M., & Chen, Y. (2015) · Journal of Composite Materials · doi:10.1177/0021998315573559 · Cited by 4
Wang, Y., Shao, L., Lastras-Montaño, M. Á., & Cheng, K.-T. T. (2019) · IEEE International Conference on Microelectronic Test Structures (ICMTS) · doi:10.1109/icmts.2019.8730924 · Cited by 4
“The D2D and C2C variations are the results of the intrinsically stochastic resistance switching mechanism of the memristors [5], [6], whereas the sneak-path problem is caused by the parasitic currents that result while accessing a single device in 1TnR ReRAM crossbars [7], as depicted in Fig.”
Background16-Bit Fixed-Point Number Multiplication With CNT Transistor Dot-Product Engine
Kim, S., Lee, Y., Kim, H., & Choi, S. (2020) · IEEE Access · doi:10.1109/access.2020.3009637 · Cited by 4
“Considering that R acc of recent resistive devices can be suppressed below 1% [16], our technique enables a reliable 16-bit precision multiplication without any error.”
BackgroundMethodArtificial Neural Networks in Hardware
Zheng, N., & Mazumder, P. (2019) · doi:10.1002/9781119507369.ch3 · Cited by 4
TCAM-GNN: A TCAM-Based Data Processing Strategy for GNN Over Sparse Graphs
Wang, Y.-P., Wang, W.-C., Chang, Y.-H., Tsai, C.-L., Kuo, T., Wu, C.-F., Ho, C.-C., & Hu, H.-W. (2023) · IEEE Transactions on Emerging Topics in Computing · doi:10.1109/tetc.2023.3328008 · Cited by 3
“For each crossbar matrix in the FF subarray, the ReRAM cell is set to 5-bit [1].”
MethodNon-linear reconfigurable threshold logic gates based on nanostructured metallic films
Martini, G., Paroli, B., & Milani, P. (2025) · npj Unconventional Computing · doi:10.1038/s44335-025-00037-1 · Cited by 4
“…of non-linear weights does not overcome all limits of the linear TLG: if the weights in W are constrained to be positive real numbers (super-linear Receptron, central circle in Fig.2) only 6 more functions, 46 ; 56 ; 78 ; 92 ; 114 ; 116 f g ; becomeimplementablewithrespectto the linear case.”
Synapse device based neuromorphic system for biomedical applications
Cho, S., Lee, C., & Lee, D. (2024) · Biomedical Engineering Letters · doi:10.1007/s13534-024-00392-1 · Cited by 3
“…implementation of DNNs, a variety of synapse devices have been introduced, leveraging advanced memory technologies such as resistive switching random access memory (RRAM), phase change memory (PCM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM) [4–7].”
Lin, Y., Zhang, Q., Gao, B., Tang, J., Zhao, H., Qin, Q., Wang, Z., Qian, H., & Wu, H. (2024) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2024.3497917 · Cited by 3
A Pragmatic Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement
Ntinas, V. G., Rubio, A., Sirakoulis, G. C., & Cotöfană, S. (2019) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2019.8702792 · Cited by 3
“However, device variability immunity has been also enabled by variability tolerant methods and architectures [9]–[11].”
BackgroundMemristor-based in-memory logic and its application in image processing
Haj-Ali, A., Ronen, R., Ben-Hur, R., Wald, N., & Kvatinsky, S. (2020) · Elsevier eBooks · doi:10.1016/b978-0-08-102782-0.00007-1 · Cited by 3
Liu, G., Hu, M., Zhang, Y., Du, E., & Liu, D. (2020) · IEICE Electronics Express · doi:10.1587/elex.17.20200273 · Cited by 3
“The state-of-the-art fabrication result has shown the 6-bit [24] to 7-bit [25] ReRAM programmable resistance level.”
BackgroundLin, Y., Tang, J., Gao, B., Zhang, Q., Qian, H., & Wu, H. (2022) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2022.3231471 · Cited by 3
“To address this issue, Alibart et al. [13] proposed a widely used iterative closed-loop feedback scheme to modulate memristors.”
BackgroundOn the HW Design of a Memory Control Unit Oriented to the Resistive Memory Technology
Carrasco, P., & Vourkas, I. (2024) · Panhellenic Conference on Electronics & Telecommunications (PACET) · doi:10.1109/pacet60398.2024.10497050 · Cited by 3
“Relevant works have highlighted the requirement for incremental amplitudes for the WRITE pulses in supervised WRITE procedures [13] to overcome soft errors , such as insufficient transitions during SET or RESET, and to achieve similar operating ranges in all the memristive cells of a ReRAM.”
BackgroundEfficient Model Switching in RRAM-Based DNN Accelerators
Gu, F.-Y., Lin, I.-C., Li, B., Schlichtmann, U., & Zhang, G. L. (2025) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2025.3550403 · Cited by 3
“To address this problem, Chen et al. [11] proposed a block-based multi-line programming (BMLP) algorithm within a hierarchical block-based programming architecture to selectively program only the necessary RRAM devices, thereby enhancing efficiency.”
Investigation of Neural Networks Using Synapse Arrays Based on Gated Schottky Diodes
Lim, S., Kwon, D., Lee, S., Kim, H., Bae, J., & Lee, J. (2019) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2019.8851691 · Cited by 3
“In order to map the trained weights to the conductance, conductance tuning methods inspired by incremental step pulse programming (ISPP) are widely employed [7], [8].”
MethodNeuromorphic circuits on segmented crossbar architectures with enhanced properties
Ntinas, V. G., Karakolis, P., Sirakoulis, G. C., & Dimitrakis, P. (2020) · European Conference on Circuit Theory and Design · doi:10.1109/ecctd49232.2020.9218289 · Cited by 3
“Such a method is described below, achieving multi-level ReRAM Ti0 2 memory programming with an accuracy of 1% of the region’s potential [13].”
MethodFast computation with memory circuit elements
Ventra, M. D., & Pershin, Y. V. (2012) · International Workshop on Cellular Nanoscale Networks and their Applications (CNNA) · doi:10.1109/cnna.2012.6331429 · Cited by 3
“…2013 [7], several other emergent applications have been recently discussed in the literature including biologically-inspired electronics [8], [9], [10], programmable analog circuits [11], [12], logic [13], [14], [15], neuromorphic and analog computation architectures [15], [16], [17], [18], [19].”
BackgroundMemristive Circuits for LDPC Decoding
Poikonen, J. H., Lehtonen, E., Laiho, M., & Poikonen, J. K. (2014) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2014.2361071 · Cited by 3
“Note that memristor programming with less than 1% error has been demonstrated empirically for example in [25] with target resistances of order .”
BackgroundMethodA thermal adaptive scheme for reliable write operation on RRAM based architectures
Garćıa-Redondo, F., López‐Vallejo, M., & Ituero, P. (2015) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd.2015.7357126 · Cited by 3
“To achieve specific accuracy for multilevel systems under variability algorithm-based drivers have been proposed [18], [19].”
BackgroundFPGA-based training and recalling system for memristor synapses
Truong, S. N., Pham, K. V., Yang, W., Song, J.-S., Mo, H.-S., & Min, K. (2016) · International Conference on Electronics, Information, and Communication (ICEIC) · doi:10.1109/elinfocom.2016.7563016 · Cited by 3
Memristors divide to conquer device variability
Fey, D. (2018) · Nature Electronics · doi:10.1038/s41928-018-0123-z · Cited by 3
Structural exploration of stochastic neural networks for severely-constrained 3D memristive devices
Achararit, P., Hida, I., Marukame, T., Asai, T., & Hara–Azumi, Y. (2018) · Nonlinear Theory and Its Applications IEICE · doi:10.1587/nolta.9.466 · Cited by 3
Making the Fault-Tolerance of Emerging Neural Network Accelerators Scalable
Liu, T., & Wen, W. (2019) · doi:10.1109/iccad45719.2019.8942073 · Cited by 3
“We follow [40] to simulate the memristive accelerator: each layer of an DNN model is mapped to one or more 128×128 arrays and each memristive cell maintains 64 quantization levels (6-bit) to strike a good balance between throughput and reliability [41].”
MethodNeko: a Library for Exploring Neuromorphic Learning Rules
Zhao, Z., Wycoff, N., Getty, N., Stevens, R. L., & Xia, F. (2021) · International Conference on Neuromorphic Systems (ICONS) · doi:10.1145/3477145.3477155 · Cited by 3
“Although training with backpropagation on device is theoretically possible, the time consumption of tuning individual weights with feedback algorithm can be prohibitive, especially for larger scale neural networks [4].”
MethodSSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM Modes
Wang, F., Sun, G., & Luo, G. (2021) · doi:10.1109/iccad51958.2021.9643493 · Cited by 3
Nili, H., Adam, G. C., Prezioso, M., Kim, J., Merrikh-Bayat, F., Kavehei, O., & Strukov, D. B. (2016) · arXiv (Cornell University) · doi:10.48550/arxiv.1611.07946 · Cited by 3
Self-citationWijesinghe, P., Ankit, A., Sengupta, A., & Roy, K. (2017) · arXiv (Cornell University) · doi:10.48550/arxiv.1712.01472 · Cited by 4
Gaussian Process for Nonlinear Regression via Memristive Crossbars
Zoppo, G., Korkmaz, A., Marrone, F., Yi, S., Palermo, S. M., Corinto, F., & Williams, R. S. (2023) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas46773.2023.10181785 · Cited by 2
“The memristor precision is selected to be 4-bits to demonstrate the invulnerability of the proposed system even though it is demonstrated that both low and high resistance memristors can be programmed to > 6 − bits precision [8], [11]–[13].”
BackgroundCai, X., Yang, Z., Wu, C., & Song, L. (2025) · Physica Scripta · doi:10.1088/1402-4896/adb45d · Cited by 2
A memristive neural decoder for cryogenic fault-tolerant quantum error correction
Yon, V., Marcotte, F., Mouny, P.-A., Dagnew, G. A., Kulchytskyy, B., Rochette, S., Beilliard, Y., Drouin, D., & Ronagh, P. (2025) · Quantum Science and Technology · doi:10.1088/2058-9565/adc3ba · Cited by 10
Efficient Reprogramming of Memristive Crossbars for DNNs: Weight Sorting and Bit Stucking
Farias, M., & Kung, H. T. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11043370 · Cited by 2
Technology considerations for neuromorphic computing
Mountain, D. J. (2016) · IEEE International Conference on Rebooting Computing (ICRC) · doi:10.1109/icrc.2016.7738688 · Cited by 2
“The 1T1M design with an access transistor enables higher precision when programming the memristors [9, 10], and also can be used to minimize power by gating the inputs if desired.”
MethodTongyu, W. A. N. G., Ran, H., & Zhou, G. (2023) · Journal of Inorganic Materials · doi:10.15541/jim20220721 · Cited by 2
Analysis of Conductance Variability in RRAM for Accurate Neuromorphic Computing
Aziza, H., Postel-Pellerin, J., Fieback, M., Hamdioui, S., Xun, H., Taouil, M., Castellani-Coulié, K., & Rahajandraibe, W. (2024) · IEEE Latin American Test Symposium (LATS) · doi:10.1109/lats62223.2024.10534620 · Cited by 2
“…to map synaptic weights is addressed [14], outcomes derived from this study can be applied to any mapping technique currently used to implement RRAM-based NN accelerators, namely, (a) multilevel [15,16], (b) binary [17], (c) unary [18], (d) multilevel with redundancy [19] and (e) slicing [8].”
MethodSribhuvaneshwari, H., & Suthendran, K. (2020) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-019-01576-x · Cited by 2
Signals generated in memristive circuits
Sowa, A. (2012) · Nanoscale Systems Mathematical Modeling Theory and Applications · doi:10.2478/nsmmt-2012-0004 · Cited by 2
“in [1] the authors proposed a device based on a layered Au-Pt-TiO2−x-Pt-Ti-SiO2-Si nano-structure1 with voltage-pulse-tunable resistive states.”
BackgroundAnalog memory characteristics of 1T1R MoOx resistive random access memory
Jo, M., Katsumura, R., Tsurumaki‐Fukuchi, A., 有田正志, Takahashi, Y., Ando, H., & Morie, T. (2016) · IEEE Silicon Nanoelectronics Workshop · doi:10.1109/snw.2016.7577993 · Cited by 2
“However, only few verification methods to achieve target resistance for analog memory have been demonstrated [3].”
BackgroundMerrikh‐Bayat, F., Merrikh-Bayat, F., & Mirebrahimi, N. (2012) · International Conference on Computer Systems and Industrial Informatics (ICCSII) · doi:10.1109/iccsii.2012.6454318 · Cited by 2
“It concludes that in practice the memristance of a memristor can be adjusted to the desired value by applying a suitable alternating-polarity voltage to it [13] (note that in practice the memristance of memristive devices always lies between two limiting values denoted as R1 and R2, where R1 R2).”
BackgroundYamamori, S., Hiromoto, M., & Sato, T. G. (2018) · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · doi:10.1587/transfun.e101.a.1092 · Cited by 2
Resistive Switching Behavior seen from the Energy Point of View
Gomez, J. T., Hoffman, A. C. A., Vourkas, I., & Rubio, A. (2018) · IEEE International On-Line Testing Symposium (IOLTS) · doi:10.1109/iolts.2018.8474167 · Cited by 2
An Analogue-Domain, Switch-Capacitor-Based Arithmetic-Logic Unit
Serb, A., & Prodromakis, T. (2019) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2019.8702070 · Cited by 2
Neuromorphic Computing Systems: From CMOS To Emerging Nonvolatile Memory
Yang, C., Qiao, X., & Chen, Y. (2019) · IPSJ Transactions on System and LSI Design Methodology · doi:10.2197/ipsjtsldm.12.53 · Cited by 2
“in the presence of large variations in switching behavior [92].”
BackgroundMemristive Computational Amplifiers and Equation Solvers
Raj, P. M. P., Kalita, A. R., & Kundu, S. (2020) · Lecture notes in electrical engineering · doi:10.1007/978-981-15-4775-1_9 · Cited by 2
Resonant Activation of Resistive Switching in ZrO2(Y) Based Memristors
Baranova, V. N., Филатов, Д. О., Александрович, А. Д., Antonov, I. N., & Gorshkov, O. N. (2020) · Semiconductors · doi:10.1134/s1063782620140031 · Cited by 2
HPM: High-Precision Modeling of a Low-Power Inverter-Based Memristive Neural Network
Mohajeri, N., Ebrahimi, B., & Dousti, M. (2021) · Journal of Circuits Systems and Computers · doi:10.1142/s0218126621502741 · Cited by 2
Anbalagan, P., Raja, R., & Hınçal, E. (2022) · Elsevier eBooks · doi:10.1016/b978-0-32-390089-8.00013-1 · Cited by 2
Planar CBRAM devices using non-cleanroom techniques as RF switches
Mahato, P., Purushothama, J. M., Vena, A., & Perret, E. (2023) · Applied Physics A · doi:10.1007/s00339-023-06687-x · Cited by 2
“The main requirements in RF switches are linearity, power handling capability and switching speed compared to read–write speed in the memories [22, 28].”
BackgroundDesign Space Evaluation of a Memristor Crossbar Based Multilayer Perceptron for Image Processing
Yakopcic, C., Fernando, B. R., & Taha, T. M. (2019) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2019.8852005 · Cited by 2
Su, P.-C., Jiang, C.-M., Chen, Y., Wang, C., Li, K., Lin, C., & Wang, T. (2019) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2019.2953781 · Cited by 2
“9 shows a measured two-stage conductance evolution in a log–log scale and its fitting results by using a power-law function [15], [16], a stretched”
BackgroundMethodPerovskites for phototunable memories and neuromorphic computing
Chen, J., Wang, Z., Wang, Y., Zhou, Y., & Han, S. (2020) · Elsevier eBooks · doi:10.1016/b978-0-12-819717-2.00012-6 · Cited by 2
Design of reconfigurable MEMS-PLL for high end turning circuits
Hanusha, A., Anusooya, S., Anitha, R., Shilpa, V. J., & Kalaivani, S. (2021) · 3C Tecnología_Glosas de innovación aplicadas a la pyme · doi:10.17993/3ctecno.2021.specialissue8.553-565 · Cited by 2
Power Profile Obfuscation using RRAMs to Counter DPA Attacks
Khedkar, G. (2013) · RIT Scholar Works (Rochester Institute of Technology) · Cited by 2
Mixed Signal Neurocomputing Based on Floating-gate Memories
Guo, X. (2017) · eScholarship (California Digital Library) · Cited by 2
Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network
Shintani, M., Ishizaka, M., & Inoue, M. (2021) · Proceedings - Asian Test Symposium/Proceedings · doi:10.1109/ats52891.2021.00017 · Cited by 1
A Novel Reliability Assessment Scheme for Nano Resistive Random Access Memory (RRAM) Testing
Sribhuvaneshwari, H., & Suthendran, K. (2022) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-022-02007-0 · Cited by 1
“1). low power adaptive write circuit is used due to its attractive features such as fast operation, less power utility and higher accuracy of write operation than different write schemes like Fixed-Length Pulse (FLP) [40], Adaptive 1T1R [41], Adaptive Single Cell [42] and High Precision Tuning [43].”
MethodIMSSA: Deploying modern state-space models on memristive in-memory compute hardware
Siegel, S., Yang, M.-J., & Strachan, J. (2024) · International Symposium on Circuits and Systems · doi:10.1109/iscas56072.2025.11043527 · Cited by 2
“However, most of these approaches suffer from inherent write noise or require complex write schemes to achieve high programming accuracies [21]–[27].”
Biologically-informed excitatory and inhibitory ratio for robust spiking neural network training
Kilgore, J. A., Kopsick, J. D., Ascoli, G. A., & Adam, G. C. (2025) · Scientific Reports · doi:10.1038/s41598-025-03408-7 · Cited by 1
“While significant progress in algorithmic solutions has been made to support highly precise programmability 16,17 these come at the cost of additional hardware overhead.”
Improved Memristor Control using Device Physics and Deep Reinforcement Learning
Yang, M.-J., Yu, Z., Pedretti, G., Neftci, E. O., & Strachan, J. P. (2025) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas64808.2025.11173161 · Cited by 2
“Specifically, hardware-fitted tuning algorithms employing active feedback schemes have been investigated to fine-tune passive memristive arrays [16] and neuromorphic learning circuits [5].”
Garg, N., Balafrej, I., Palhares, J. H. Q., Bégon‐Lours, L., Florini, D., Falcone, D. F., Stecconi, T., Bragaglia, V., Offrein, B. J., Portal, J., et al. (2026) · Communications Materials · doi:10.1038/s43246-025-01033-5 · Cited by 1
“More complex situations occur when both pulse amplitude and pulse duration can be modulated during the learning signal, with the benefit of a larger dynamic range of programming and a higher number of states available [30].”
Self-citationMemristor based digital-to-analog convertor and its programming
Jahromi, M. R., Shamsi, J., Mohammadi, K., & Sabbaghi‐Nadooshan, R. (2015) · Iranian Conference on Electrical Engineering · doi:10.1109/iraniancee.2015.7146427 · Cited by 1
Siemon, A., Menzel, S., Waser, R. M., & Linn, E. (2015) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2015.7280745 · Cited by 1
Development system for memristor circuits
Faghih-Nassiri, J., Maddy, N., Buckland, L., & Strukov, D. B. (2013) · IEEE International Conference on Nanotechnology (IEEE-NANO) · doi:10.1109/nano.2013.6721014 · Cited by 1
Self-citationDynamic Response of Multiple Interconnected Memristors
Vourkas, I., & Sirakoulis, G. C. (2015) · Emergence, complexity and computation · doi:10.1007/978-3-319-22647-7_3 · Cited by 1
Hardware acceleration for neuromorphic computing: An evolving view
Liu, B., Liu, X., Liu, C., Wen, W., Meng, M., Li, H. H., & Chen, Y. (2015) · Non-Volatile Memory Technology Symposium · doi:10.1109/nvmts.2015.7457496 · Cited by 1
Domain Wall Motion-based XOR-like Activation Unit With A Programmable Threshold
Deb, S., Vatwani, T., Chattopadhyay, A., Basu, A., & Fong, X. (2018) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn.2018.8489146 · Cited by 1
“A high precision tuning algorithm [27] is executed on a dynamic switching model [28] of memristor for importing these mapped conductances to the”
MethodComparison of update and genetic training algorithms in a memristor crossbar perceptron
Edwards, K. N., & Shen, X. (2022) · AIP Advances · doi:10.1063/5.0079317 · Cited by 1
Wang, X., Wu, X., Nie, Z., & Yan, Z. (2023) · Complexity · doi:10.1155/2023/1335184 · Cited by 1
“Over the past decade or so, the research studies put more energy into such a few aspects, such as signal processing [1], intelligent vehicle [2], and chaotic circuits [3].”
BackgroundAn FPGA-Based Training System for a 1T1R Memristor Array With 500 nS Conductance Resolution Limit
Li, L., Cheng, C., Huang, B., Ding, K., Li, Y., & Guo, G. (2023) · IEEE Access · doi:10.1109/access.2023.3322034 · Cited by 1
“With the resistance of the memristor accurately measured, the next step is to increase or decrease the resistance of the memristor [36].”
BackgroundA Variation-Aware CMOS Platform for Multi-Level Memristor Characterisation
Xie, L., Feng, P., Mifsud, A., Nassibi, A., & Papavassiliou, C. (2024) · International Conference on Modern Circuits and Systems Technologies · doi:10.1109/mocast61810.2024.10615592 · Cited by 1
“Consequently, precise memristor programming demands closed-loop pulsing schemes [9]–[11] as introduced in Fig.”
BackgroundHigh-speed programming with threshold division for RRAM-based neural network accelerators
Du, X., Chen, T., Su, M., Li, Z., Tong, P., Wang, W., & Cao, R. (2024) · AIP Advances · doi:10.1063/5.0243471 · Cited by 1
Dead-zone free Memristor-based Phase-Frequency Detector for Duty-Cycled Transceivers
Elashkar, N. E., Khalil, A. H., Aboudina, M. M., Fahmy, H. A. H., & Ibrahim, G. H. (2025) · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · doi:10.1109/icecs66544.2025.11270689 · Cited by 1
“The initialization is performed by applying a DC input signal that pushes the memristor state value to the initial boundary [9], [10].”
Qualitative SPICE modeling accounting for volatile dynamics of TiO2 memristors
Berdan, R., Khiat, A., Papavassiliou, C., & Prodromakis, T. (2014) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2014.6865564 · Cited by 1
A novel memristive cellular neural network with time-variant templates
Hu, X., Chen, G., & Duan, S. (2015) · Perspectives in Science · doi:10.1016/j.pisc.2015.11.021 · Cited by 1
Energy Efficient RRAM Crossbar-Based Approximate Computing for Smart Cameras
Wang, Y., Li, B., Xia, L., Tang, T., & Yang, H. (2016) · Springer eBooks · doi:10.1007/978-3-319-33201-7_5 · Cited by 1
Processing-In-Memory Architecture Design for Accelerating Neuro-Inspired Algorithms
Chi, P., Li, S., & Xie, Y. (2017) · Springer eBooks · doi:10.1007/978-3-319-54313-0_10 · Cited by 1
Shock waves in binary oxides memristors
Rozenberg, M. J., Dobrosavljević, V., Tesler, F., & Tang, S. H. (2017) · Spintronics · doi:10.1117/12.2277977 · Cited by 1
A Comparator Design Targeted towards Neural Nets
Mountain, D. J. (2019) · IEEE International Conference on Rebooting Computing (ICRC) · doi:10.1109/icrc.2019.8914715 · Cited by 1
“The value of the 1T1M design is that the P-channel Field Effect Transistor (PFET) access device eliminates sneak path issues [10] and enables highly precise programming of memristor conductances [11].”
MethodeNVM based In-memory Computing for Intelligent and Secure Computing Systems
Huang, K., & Qin, C. (2019) · IEEE International System-on-Chip Conference (SOCC) · doi:10.1109/socc46988.2019.1570557582 · Cited by 1
“• The state-of-the-art RRAM devices can only support 4 to 6 bits of resistance levels [22].”
BackgroundResonant activation of resistive switching in ZrO2(Y) based memristors
Baranova, V. N., Филатов, Д. О., Александрович, А. Д., Antonov, I. N., & Gorshkov, O. N. (2020) · Journal of Physics Conference Series · doi:10.1088/1742-6596/1695/1/012151 · Cited by 1
Merrikh‐Bayat, F., Mirebrahimi, N., & Bayat, F. (2013) · arXiv (Cornell University) · doi:10.48550/arxiv.1302.1005 · Cited by 1
“It concludes that in practice the memristance of a memristor can be adjusted to the desired value by applying a suitable alternating-polarity voltage to it [16] (note that in practice the memristance of memristive devices always lies between two limiting values denoted as on R and off R , where”
BackgroundThree-Dimensional Stateful Material Implication LogicPreprint
Adam, G. C., Hoskins, B. D., Prezioso, M., & Strukov, D. B. (2015) · arXiv (Cornell University) · doi:10.48550/arxiv.1509.02986 · Cited by 1
“Abstract Monolithic three-dimensional integration of memory and logic circuits could dramatically improve performance and energy efficiency of computing systems.(1,2) Some conventional and emerging memories are suitable for vertical integration,(3,4) including highly scalable metaloxide resistive switching devices (“m…”
BackgroundMethodSelf-citationAssessing the Performance of Reinforcement Learning on Passive RRAM Crossbar ArrayPreprint
Tyagi, A., & Sahay, S. (2023) · doi:10.36227/techrxiv.22347277 · Cited by 1
Interfacing Memristors for Reliable Computing
Herranz, A. D. G. (2023) · doi:10.20868/upm.thesis.78885
Yoon, J. H., Jung, H., Lee, M. H., Kim, G. H., Song, S. J., Seok, J. Y., Yoon, K. J., Hwang, C. S., Besland, M., Tranchant, J., et al. (2012) · Frontiers in Electronic Materials · doi:10.1002/9783527667703.ch67
Self-citationTime Voltage Dependency in Resistance Switching TiO2
Nauenheim, C., Drouin, D., Waser, R. M., & Ruediger, A. P. (2012) · MRS Proceedings · doi:10.1557/opl.2012.937
Metadata
- Authors
- Alibart, F., Gao, L., Hoskins, B. D., & Strukov, D. B.
- Affiliations
- University of California, Santa Barbara (US)
- Venue
- Nanotechnology
- Publisher
- IOP Publishing
- Published
- 2012-01-20
- Volume
- 23
- Issue
- 7
- Pages
- 075201
- ISSN
- 0957-4484 (ISSN-L)
- 1361-6528
- OpenAlex
- W2091777687
- Cited by
- 557
- References
- 35
- Citations by year
- 2026: 9 · 2025: 26 · 2024: 21 · 2023: 37 · 2022: 37 · 2021: 45 · 2020: 56 · 2019: 73 · 2018: 58 · 2017: 43 · 2016: 47 · 2015: 39 · 2014: 27 · 2013: 22 · 2012: 16
- FWCI
- 21.27
- Type
- journal article
- Language
- en
- Open access
- bronze
- doi.org
- Locations
- Nanotechnology (publishedVersion)
- PubMed (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- arXiv (Cornell University)
- Funders
- National Science Foundation (1028336, 1121053)
- Division of Materials Research (DMR 1121053, 1121053)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Keywords
- memristors, TiO2 thin films, resistive switching, conductance tuning, variation tolerance, filamentary switching, non-volatile memory, analog computing, dot product computation, summing amplifier
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