The DOI matches its Crossref record; 35 of the 35 references it cites were found in a registry or an index.
High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm
Open accessAbstract
Using memristive properties common for titanium dioxide thin film devices, we designed a simple write algorithm to tune device conductance at a specific bias point to 1% relative accuracy (which is roughly equivalent to seven-bit precision) within its dynamic range even in the presence of large variations in switching behavior. The high precision state is nonvolatile and the results are likely to be sustained for nanoscale memristive devices because of the inherent filamentary nature of the resistive switching. The proposed functionality of memristive devices is especially attractive for analog computing with low precision data. As one representative example we demonstrate hybrid circuitry consisting of an integrated circuit summing amplifier and two memristive devices to perform the analog multiply-and-add (dot-product) computation, which is a typical bottleneck operation in information processing.
Overview
The claims and statistics of this paper haven’t been checked yet.
Run the check — free, no account needed. It reads the open-access text and checks the sources it cites.
Integrity signals
Registry
Cites
Statistics
Verification
Claims the paper makes
The claims and statistics of this paper haven’t been checked yet.
Run the check — free, no account needed. It reads the open-access text and checks the sources it cites.
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
The cited source says what the claim attributes to it.
In the citing paper
“To program an RRAM cell to its target conductance, we use an incremental-pulse write–verify technique42.”
From A compute-in-memory chip based on resistive random-access memory (2022) · cites this paper as [42]
Self-check
Percentages, sums and reported differences re-computed from the paper’s own numbers.
The self-check needs the paper’s full text.
Citations
Cites
Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges
Waser, R., Dittmann, R., Staikov, G., & Szot, K. (2009) · Advanced Materials · doi:10.1002/adma.200900375 · Cited by 5,080
Nanoscale Memristor Device as Synapse in Neuromorphic Systems
Jo, S. H., Chang, T., Ebong, I., Bhadviya, B. B., Mazumder, P., & Lu, W. (2010) · Nano Letters · doi:10.1021/nl904092h · Cited by 4,174
Memristive switching mechanism for metal/oxide/metal nanodevices
Yang, J. J., Pickett, M. D., Li, X., Ohlberg, D. A. A., Stewart, D. R., & Williams, R. S. (2008) · Nature Nanotechnology · doi:10.1038/nnano.2008.160 · Cited by 2,987
Resistive switching in transition metal oxides
Sawa, A. (2008) · Materials Today · doi:10.1016/s1369-7021(08)70119-6 · Cited by 2,949
Atomic structure of conducting nanofilaments in TiO2 resistive switching memory
Kwon, D.-H., Kim, K. M., Jang, J. H., Jeon, J. M., Lee, M. H., Kim, G. H., Li, X.-S., Park, G.-S., Lee, B., Han, S., et al. (2010) · Nature Nanotechnology · doi:10.1038/nnano.2009.456 · Cited by 2,092
Resistance switching memories are memristors
Chua, L. (2011) · Applied Physics A · doi:10.1007/s00339-011-6264-9 · Cited by 1,434
Reproducible switching effect in thin oxide films for memory applications
Beck, A., Bednorz, J. G., Gerber, C., Rossel, C., & Widmer, D. (2000) · Applied Physics Letters · doi:10.1063/1.126902 · Cited by 1,129 · cited 1×
“However, for all other applications, e.g., multilevel memory [Bec00, Yu11a, Cho06], configurable filters [Dri10], and analog computing circuits (see, e.g., various theoretical proposals in Refs.”
BackgroundMemory effects in complex materials and nanoscale systems
Pershin, Y. V., & Di Ventra, M. (2011) · Advances In Physics · doi:10.1080/00018732.2010.544961 · Cited by 823
Yu, S., Wu, Y., Jeyasingh, R., Kuzum, D., & Wong, H.-S. P. (2011) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2011.2147791 · Cited by 805
Switching dynamics in titanium dioxide memristive devices
Pickett, M. D., Strukov, D. B., Borghetti, J. L., Yang, J. J., Snider, G. S., Stewart, D. R., & Williams, R. S. (2009) · Journal of Applied Physics · doi:10.1063/1.3236506 · Cited by 775
Self-citation
Research works printed but not linked: 7
- Kim K M, 2011, Nanotechnology, 22
- Lee J Park J Jung S Hwang H, 2011, Proc. Int. Technology Conf. and Materials for Advanced Metallization, 1
- Papandreou N Pozidis H Pantazi A Sebastian A Breitwisch M Lam C Eleftheriou E, 2011, Proc. IEEE Int. Symp. on Circuits and Systems, 329
- Prodromakis T Toumazou C, 2010, Proc. IEEE Int. Conf. on Electronics, Circuits, and Systems, 934
- Seo K, 2011, Nanotechnology, 22
- Snider G S, 2007, Nanotechnology, 18
- Strachan J P, 2011, Nanotechnology, 22
Cited by
Sorted by citations
Items 201–300 of 557
Memristor-based perceptron classifier: Increasing complexity and coping with imperfect hardware
Bayat, F. M., Prezioso, M., Chakrabarti, B., Kataeva, I., & Strukov, D. (2017) · 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) · doi:10.1109/iccad.2017.8203825 · Cited by 29
“However, though the write-verify algorithm [19] circumvents the problem of threshold variations in memristors, such ex-situ approach cannot cope with other imperfections in the hardware, such as stuck-close or stuck-open defects (Fig.”
BackgroundSelf-citationMemristors for neural branch prediction
Saadeldeen, H., Franklin, D. M., Long, G., Hill, C., Browne, A., Strukov, D. B., Sherwood, T., & Chong, F. T. (2013) · ACM International Conference on Computing Frontiers (CF) · doi:10.1145/2482767.2482801 · Cited by 25
“3) with weights of up to 7-bit precision [5].”
BackgroundInfluentialSelf-citationVourkas, I., & Sirakoulis, G. (2014) · Microelectronics Journal · doi:10.1016/j.mejo.2014.08.004 · Cited by 22
“We note here that, although single memristors could be switched to all intermediate conducting states by using appropriate biasing [39], their behavior is strongly dependent on device variations and thus stable operation cannot be guaranteed.”
BackgroundNew pulse amplitude modulation for fine tuning of memristor synapses
Truong, S. N., Pham, K. V., Yang, W., Shin, S., Pedrotti, K. D., & Min, K. (2016) · Microelectronics Journal · doi:10.1016/j.mejo.2016.07.010 · Cited by 25
Memristor-Based Variation-Enabled Differentially Private Learning Systems for Edge Computing in IoT
Fu, J., Liao, Z., Liu, J., Smith, S. C., & Wang, J. (2020) · IEEE Internet of Things Journal · doi:10.1109/jiot.2020.3023623 · Cited by 25
“Among all variations of memristors not attributed to manufacturing process, cycle-to-cycle variation is caused by intrinsically stochastic resistance switching mechanisms [25]–[28] that can be approximated as a Gaussian or normal distribution [19], [20], [29]–[33].”
BackgroundLiu, L., Ni, Y., Liu, J., Wang, Y., Jiang, C., & Xu, W. (2022) · Advanced Functional Materials · doi:10.1002/adfm.202210119 · Cited by 26
Synaptic Weight States in a Locally Competitive Algorithm for Neuromorphic Memristive Hardware
Woods, W., Bürger, J., & Teuscher, C. (2015) · IEEE Transactions on Nanotechnology · doi:10.1109/tnano.2015.2449835 · Cited by 26
Choi, S., Bezugam, S. S., Bhattacharya, T., Kwon, D., & Strukov, D. B. (2025) · Nature Communications · doi:10.1038/s41467-025-63831-2 · Cited by 24
“The primary approach to implementing multiple conductance states is to systemically control the growth dynamics of the switching fi lament using a tuning algorithm based on an incremental programming voltage scheme 49 .”
Self-citationShock Waves and Commutation Speed of Memristors
Tang, S., Tesler, F., Marlasca, F. G., Levy, P., Dobrosavljević, V., & Rozenberg, M. J. (2016) · Physical Review X · doi:10.1103/physrevx.6.011028 · Cited by 24
Intrinsic Bounds for Computing Precision in Memristor-Based Vector-by-Matrix Multipliers
Mahmoodi, M. R., Vincent, A. F., Nili, H., & Strukov, D. B. (2020) · IEEE Transactions on Nanotechnology · doi:10.1109/tnano.2020.2992493 · Cited by 24
“In case of ideal, linear devices, the slope of I-V curve, i.e., the memory state, is typically assessed by measuring device current at the highest operating voltage ( U max ), when using write-verify tuning algorithm [13].”
BackgroundMethodSelf-citationOn memristor ideality and reciprocity
Georgiou, P. S., Barahona, M., Yaliraki, S. N., & Drakakis, E. M. (2014) · Microelectronics Journal · doi:10.1016/j.mejo.2014.08.003 · Cited by 24
“In the case of memristors, we may arrive at the same conclusion following an alternative path: Chua’s Closure and Existence and Uniqueness theorems show that a network of ideal memristors is equivalent to a single unique memristor [1].”
BackgroundInfluentialAnalog and bipolar resistive switching in pn junction of n-type ZnO nanowires on p-type Si substrate
Lee, S. C., Hu, Q., Baek, Y.-J., Choi, Y. J., Kang, C. J., Lee, H. H., & Yoon, T. (2013) · Journal of Applied Physics · doi:10.1063/1.4817838 · Cited by 24
A heterogeneous computing system with memristor-based neuromorphic accelerators
Liu, X., Mao, M., Li, H. H., Chen, Y., Jiang, H., Yang, J. J., Wu, Q., & Barnell, M. D. (2014) · IEEE High Performance Extreme Computing Conference · doi:10.1109/hpec.2014.7040986 · Cited by 23
“Recent research shows that the memristor resistance can be precisely programmed [28][33] to realize an 8-bit precision on a single memristor cell [5].”
BackgroundMethodAnsari, M., Fayyazi, A., BanaGozar, A., Maleki, M. A., Kamal, M., Afzali‐Kusha, A., & Pedram, M. (2017) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2017.2764070 · Cited by 24
“each individual memristor tuning, on average, 12 consecutive write pulses were needed [28] and each pulse had a duration of 1 ns.”
BackgroundMethodInfluentialZheng, X., Zarcone, R. V., Paiton, D. M., Sohn, J., Wan, W., Olshausen, B. A., & Wong, H. ‐. P. (2018) · Technical digest - International Electron Devices Meeting/Technical digest · doi:10.1109/iedm.2018.8614612 · Cited by 23
Adaptive programming in multi-level cell ReRAM
Ramadan, M., Wainstein, N., Ginosar, R., & Kvatinsky, S. (2019) · Microelectronics Journal · doi:10.1016/j.mejo.2019.06.004 · Cited by 23
“2, have been reported in the literature, including staircase programming [4], [10], program and verify [4], [11], self-controlled programming [12], and time-domain state control [13].”
BackgroundMethodSun, B. T., Guo, T., Zhou, G., Ranjan, S., Hou, W., Hou, Y., & Zhao, Y. X. (2019) · Journal of Colloid and Interface Science · doi:10.1016/j.jcis.2019.06.076 · Cited by 23
Synaptic Function in Memristor Devices for Neuromorphic Circuit Applications
Bisquert, J., Shim, W., Kim, S., & Linares-Barranco, B. (2025) · Advanced Electronic Materials · doi:10.1002/aelm.202400903 · Cited by 23
Nonvolatile Multilevel Resistive Switching Memory Cell: A Transition Metal Oxide-Based Circuit
Stoliar, P., Lévy, P., Sánchez, M. J., Leyva, A. G., Albornoz, C. A., Gomez-Marlasca, F., Zanini, A., Salazar, C. T., Ghenzi, N., & Rozenberg, M. J. (2014) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2013.2290921 · Cited by 22
HR3AM: A Heat Resilient Design for RRAM-based Neuromorphic Computing
Liu, X., Zhou, M., Rosing, T., & Zhao, J. (2019) · International Symposium on Low Power Electronics and Design (ISLPED) · doi:10.1109/islped.2019.8824926 · Cited by 22
“Single cell only achieves at most seven bits accuracy [3].”
BackgroundNeural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals
Cao, W., Zhao, Y., Boloor, A., Han, Y., Zhang, X., & Jiang, L. (2021) · IEEE Transactions on Computers · doi:10.1109/tc.2021.3122905 · Cited by 23
“4, as the buffer array RRAM cell requires precision > 7-bit 1 when P D ≥ 2, beyond the ability that state-of-the-art fabricated device can achieve [38].”
BackgroundLin, P., Chen, K., Chaurasiya, R., Le, H., Cheng, C., Lu, D. D., & Chen, J. (2023) · Advanced Functional Materials · doi:10.1002/adfm.202307961 · Cited by 22
Kim, H., Bae, J., Lim, S., Lee, S., Seo, Y.-T., Kwon, D., Park, B., & Lee, J. (2019) · Neurocomputing · doi:10.1016/j.neucom.2019.09.099 · Cited by 22
Zhou, Y., Hu, X., Wang, L., Zhou, G., & Duan, S. (2021) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2021.3115787 · Cited by 22
Tosson, A. M. S., Yu, S., Anis, M. H., & Wei, L. (2017) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2017.2734819 · Cited by 23
Review of neuromorphic computing based on NAND flash memory
Lee, S., & Lee, J.-H. (2024) · Nanoscale Horizons · doi:10.1039/d3nh00532a · Cited by 21
Jeong, H., Han, S., Park, S., Kim, T. R., Bae, J., Jang, T., Cho, Y., Seo, S., Jeong, H.-J., Park, S., et al. (2025) · Nature Electronics · doi:10.1038/s41928-024-01318-6 · Cited by 23
“At the software level, compensation algorithms such as a write-and-verification programming scheme or in situ training from a pretrained weight have been used to reduce the accuracy degradation 24,25 .”
Challenges of memristor based neuromorphic computing system
Yan, B., Chen, Y., & Li, H. H. (2018) · Science China Information Sciences · doi:10.1007/s11432-017-9378-3 · Cited by 21
A Self-Test Framework for Detecting Fault-induced Accuracy Drop in Neural Network Accelerators
Meng, F., Hosseini, F. S., & Yang, C. (2021) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1145/3394885.3431519 · Cited by 21
“For instance, programming of an RRAM cell does not set the conductance to the expected value, but rather on a normal distribution within the objective range [1].”
BackgroundLong Short-Term Memory Implementation Exploiting Passive RRAM Crossbar Array
Nikam, H., Satyam, S., & Sahay, S. (2021) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2021.3133197 · Cited by 21
Analog Solutions of Discrete Markov Chains via Memristor Crossbars
Zoppo, G., Korkmaz, A., Marrone, F., Palermo, S. M., Corinto, F., & Williams, R. S. (2021) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2021.3126477 · Cited by 21
“At the time of writing, the best experimental results available in the literature reported up to 256 (8 bits) reliably programmable conductance levels [29].”
BackgroundLee, S., & Lee, J. (2023) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2023.3237670 · Cited by 21
Heittmann, A., & Noll, T. G. (2012) · ACM Great Lakes Symposium on VLSI (GLSVLSI) · doi:10.1145/2206781.2206836 · Cited by 21
A novel design of memristor-based bidirectional associative memory circuits using Verilog-AMS
Li, B., Zhao, Y., & Shi, G. (2018) · Neurocomputing · doi:10.1016/j.neucom.2018.11.050 · Cited by 21
Woods, W., & Teuscher, C. (2018) · IEEE Transactions on Neural Networks and Learning Systems · doi:10.1109/tnnls.2018.2878002 · Cited by 20
Chang, C.-C., Wu, M.-H., Lin, J., Li, C., Parmar, V., Lee, H.-Y., Wei, J., Sheu, S.-S., Suri, M., Chang, T., et al. (2019) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1145/3316781.3317872 · Cited by 20
“The placement variation has to be precisely controlled within 1 % by using time-consuming iterative write-and-verify methods [20].”
MethodVoltage Divider for Self-Limited Analog State Programing of Memristors
Gomez, J. T., Vourkas, I., Hoffman, A. C. A., Sirakoulis, G. C., & Rubio, A. (2019) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2019.2923716 · Cited by 20
“several strategies/circuits and different adaptive pulsing protocols/algorithms have been proposed in the literature to improve the controllability of multi-level (ML) resistive states [7]–[11]”
BackgroundMethodInfluentialTraining low bitwidth convolutional neural network on RRAM
Cai, Y., Tang, T., Xia, L., Cheng, M., Zhu, Z., Wang, Y., & Yang, H. (2018) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1109/aspdac.2018.8297292 · Cited by 20
“Only 7-bit precision is achievable on state-of-the-art RRAM device [9].”
MethodMemory Technologies for Neural Networks
Strukov, D. B., Merrikh-Bayat, F., Prezioso, M., Guo, X., Hoskins, B. D., & Likharev, K. K. (2015) · IEEE International Memory Workshop (IMW) · doi:10.1109/imw.2015.7150295 · Cited by 18
“3e), using a simple, fully automated feedback procedure that had been originally developed for tuning memristors [21].”
MethodSelf-citationCharacteristics of Resistive Memory Read Fluctuations in Endurance Cycling
Nminibapiel, D., Veksler, D. B., Shrestha, P. R., Kim, J.-H., Campbell, J. P., Ryan, J. T., Baumgart, H., & Cheung, K. P. (2017) · IEEE Electron Device Letters · doi:10.1109/led.2017.2656818 · Cited by 19
“Demonstrations of precise resistance state control [4], [5] further extended the application space to include multilevel cells and neuromorphic computing.”
BackgroundRescuing RRAM-Based Computing From Static and Dynamic Faults
Lin, J., Wen, C.-D., Hu, X., Tang, T., Lin, I.-C., Wang, Y., & Xie, Y. (2020) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2020.3037316 · Cited by 19
Improved multi-level control of RRAM using pulse-train programming
Zhao, L., Chen, H.-Y., Wu, S.-C., Jiang, Z., Yu, S., Hou, T., Wong, H. ‐. P., & Nishi, Y. (2014) · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · doi:10.1109/vlsi-tsa.2014.6839673 · Cited by 19
Neuron Model with Simplified Memristive Ionic Channels
Hegab, A. M., Salem, N. M., Radwan, A. G., & Chua, L. O. (2015) · International Journal of Bifurcation and Chaos · doi:10.1142/s0218127415300177 · Cited by 19
Falcone, D. F., Clerico, V., Choi, W., Stecconi, T., Horst, F., Bégon‐Lours, L., Galetta, M., Porta, A. L., Garg, N., Alibart, F., et al. (2025) · Advanced Functional Materials · doi:10.1002/adfm.202504688 · Cited by 18
“Unlike the conventional incremental-pulse closed-loop technique previously used for ReRAM [9, 43], where the amplitudes of set and reset pulses are gradually increased to achieve convergence, this work employs an identical-pulse closed-loop scheme to simplify the pulse generation circuitry design,…”
Self-citationFPAA/Memristor Hybrid Computing Infrastructure
Laiho, M., Hasler, J., Zhou, J., Du, C., Lu, W. D., Lehtonen, E., & Poikonen, J. H. (2015) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2014.2386773 · Cited by 18
Highly Reliable Inference System of Neural Networks Using Gated Schottky Diodes
Lim, S., Kwon, D., Eum, J.-H., Lee, S., Bae, J., Kim, H., Kim, C.-H., Park, B., & Lee, J. (2019) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2019.2913146 · Cited by 18
“Although the read-write-verify scheme can also be used for precise tuning in off-chip training [27], it is more complicated method compared to the method using an index number [28].”
MethodDesign of memristor based low power and highly reliable ReRAM cell
Pal, S., Bose, S., & Islam, A. (2019) · Microsystem Technologies · doi:10.1007/s00542-019-04582-1 · Cited by 18
Neuromorphic computing: From devices to integrated circuits
Saxena, V. (2020) · Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena · doi:10.1116/6.0000591 · Cited by 20
Yan, Z., Juan, D.-C., Hu, X. S., & Shi, Y. (2021) · Proceedings of the 26th Asia and South Pacific Design Automation Conference · doi:10.1145/3394885.3431635 · Cited by 18
“Write-and-verify [1, 15, 19] is a simple, accurate and widely used programming scheme for RRAMs.”
MethodMemristors Based on 2D Materials: Bridging Device Theory and Potential Applications
Liu, X., Pan, Z., Xia, Z., Li, L., Deng, Q., Pan, Y., Li, J., & Huo, N. (2025) · Advanced Functional Materials · doi:10.1002/adfm.202520816 · Cited by 19
A novel ReRAM-based processing-in-memory architecture for graph computing
Han, L., Shen, Z., Shao, Z., Huang, H. H., & Li, T. (2017) · IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) · doi:10.1109/nvmsa.2017.8064464 · Cited by 17
“The next step is to attain the adjacent vertices of V ertex 5 from the coordinate [2, 2] to [3, 1] in crossbar by activating wordline No.”
BackgroundPost-silicon nano-electronic device and its application in brain-inspired chips
Lv, Y., Chen, H., Wang, Q., Li, X., Xie, C., & Song, Z. (2022) · Frontiers in Neurorobotics · doi:10.3389/fnbot.2022.948386 · Cited by 17
“For a single Pt/TiO2−x/Pt device, this method can adjust the conductance to any expected value in the dynamic range of the device with an error of only 1% (Alibart et al., 2011).”
BackgroundMethod(2022) · Springer eBooks · doi:10.1007/978-3-030-90582-8 · Cited by 17
Woods, W., & Teuscher, C. (2017) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1109/nanoarch.2017.8053729 · Cited by 17
“These devices have been shown to be tunable within ±1% of a target resistance [2].”
BackgroundOptimizing Incremental Step Pulse Programming for RRAM Through Device–Circuit Co-Design
Liu, J., Wu, T.-Y., & Hou, T. (2018) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2018.2821268 · Cited by 17
“Many ISPP-inspired programming methods for both single-level-cell and multi-level-cell RRAM [11]–[18] were further developed because of the significant differences”
BackgroundChung, J., Park, J., & Ghosh, S. (2016) · International Symposium on Low Power Electronics and Design (ISLPED) · doi:10.1145/2934583.2934602 · Cited by 17
“This is a critical programming limitation in a memristor device [7].”
BackgroundA memristor-based convolutional neural network with full parallelization architecture
Sun, S., Li, Z., Li, J., Liu, H., Liu, H., & Li, Q. (2019) · IEICE Electronics Express · doi:10.1587/elex.16.20181034 · Cited by 16
“After finishing the training process, we use close-loop tuning scheme [10] to program memristors to the trained values.”
BackgroundMethodYan, M., & Jiang, M. (2020) · Neurocomputing · doi:10.1016/j.neucom.2019.12.124 · Cited by 16
All-Passive Hardware Implementation of Multilayer Perceptron Classifiers
Ananthakrishnan, A., & Allen, M. G. (2020) · IEEE Transactions on Neural Networks and Learning Systems · doi:10.1109/tnnls.2020.3016901 · Cited by 16
“Noting that the state of the art in memristor technologies can implement conductances up to a relative accuracy of 1% [18], [25], we expect passive SMLPs to achieve accuracies of around 95.3% ± 0.1% even in the presence of 1% conductance variations [see Fig.”
BackgroundInfluentialRobust neuromorphic computing in the presence of process variation
BanaGozar, A., Maleki, M. A., Kamal, M., Afzali‐Kusha, A., & Pedram, M. (2017) · Design, Automation, and Test in Europe · doi:10.23919/date.2017.7927030 · Cited by 16
Design of a memristor based fuzzy processor
Tarkhan, M., & Maymandi‐Nejad, M. (2017) · AEU - International Journal of Electronics and Communications · doi:10.1016/j.aeue.2017.10.039 · Cited by 15
Shahroodi, T., Singh, G., Zahedi, M., Mao, H., Lindegger, J., Fırtına, C., Wong, S., Mutlu, O., & Hamdioui, S. (2023) · IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1145/3613424.3614252 · Cited by 16
“the process variation that exist in memristors [4, 23, 70, 148], (3) The wire resistance and sneak paths, due to imperfect wires (i.”
BackgroundHigh throughput neural network based embedded streaming multicore processors
Hasan, R., Taha, T. M., Yakopcic, C., & Mountain, D. J. (2016) · IEEE International Conference on Rebooting Computing (ICRC) · doi:10.1109/icrc.2016.7738690 · Cited by 15
Rescuing memristor-based computing with non-linear resistance levels
Lin, J., Xia, L., Zhu, Z., Sun, H., Cai, Y., Gao, H., Cheng, M., Chen, X., Wang, Y., & Yang, H. (2018) · Design, Automation, and Test in Europe · doi:10.23919/date.2018.8342044 · Cited by 15
A high precision write/read circuits for memristors using digital input/output interfaces
Daoud, A. A., Dessouki, A. S., Mostafa, H., Abdallah, R. M., & El‐Rabaie, E. M. (2019) · Microelectronics Journal · doi:10.1016/j.mejo.2019.104694 · Cited by 15
“[30 – 32], the authors use pulses with speci fi c width and amplitude to write, read and refresh a memristor to a speci fi c memristance state.”
BackgroundMethodImplementation of Ternary Weights With Resistive RAM Using a Single Sense Operation Per Synapse
Laborieux, A., Bocquet, M., Hirtzlin, T., Klein, J., Nowak, E., Vianello, E., Portal, J., & Querlioz, D. (2020) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2020.3031627 · Cited by 14
Ratio-based multi-level resistive memory cells
Lastras-Montaño, M. Á., Pozo-Zamudio, O. D., Glebsky, L. Y., Zhao, M., Wu, H., & Cheng, K.-T. T. (2021) · Scientific Reports · doi:10.1038/s41598-020-80121-7 · Cited by 15
Composite Characteristics of Memristor Series and Parallel Circuits
Hu, X., Feng, G., Liu, L., & Duan, S. (2015) · International Journal of Bifurcation and Chaos · doi:10.1142/s0218127415300190 · Cited by 15
Chen, X., Jiang, J., Zhu, J., & Tsui, C.-Y. (2018) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1109/aspdac.2018.8297293 · Cited by 18
López-Soriano, S., Purushothama, J. M., Vena, A., & Perret, E. (2022) · Scientific Reports · doi:10.1038/s41598-022-08127-x · Cited by 14
Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges
Garćıa-Redondo, F., Royer, P., López‐Vallejo, M., Aparicio, H., Ituero, P., & Barrio, C. A. L. (2016) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2016.2634083 · Cited by 14
Kim, S., Choi, B., Yoon, J., Lee, Y., Kim, H., Kang, M., & Choi, S. (2019) · Scientific Reports · doi:10.1038/s41598-019-48048-w · Cited by 15
Evaluating Neural Network-Inspired Analog-to-Digital Conversion With Low-Precision RRAM
Cao, W., Ke, L., Chakrabarti, A., & Zhang, X. (2020) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2020.3013563 · Cited by 14
“Each NN model is trained via stochastic gradient descent with Adam optimizer [28] using TensorFlow [29] [42].”
MethodAn Efficient Programming Framework for Memristor-based Neuromorphic Computing
Zhang, G. L., Li, B., Huang, X., Shen, C., Zhang, S., Burcea, F., Graeb, H., Ho, T.-Y., Li, H. H., & Schlichtmann, U. (2021) · Design, Automation, and Test in Europe · doi:10.23919/date51398.2021.9474084 · Cited by 14
“In [20], a feedback algorithm is introduced to tune the conductances of memristors with iterative programming and reading pulses, while device variations are determined by reading operations.”
BackgroundMethodInfluentialExploiting Non-idealities of Resistive Switching Memories for Efficient Machine Learning
Yon, V., Amirsoleimani, A., Alibart, F., Melko, R. G., Drouin, D., & Beilliard, Y. (2022) · Frontiers in Electronics · doi:10.3389/felec.2022.825077 · Cited by 14
“A write-verify scheme (Papandreou et al., 2011; Yi et al., 2011; Alibart et al., 2012; Perez et al., 2017; Pan et al., 2020) typically neglects energy consumption and memory lifetime for the sake of accuracy.”
BackgroundSelf-citationXB-SIM∗: A simulation framework for modeling and exploration of ReRAM-based CNN acceleration design
Fei, X., Zhang, Y., & Zheng, W. (2020) · Tsinghua Science & Technology · doi:10.26599/tst.2019.9010070 · Cited by 14
“Thus, two cells can represent a value of 2 .b C 1/ levels (suppose a cell can represent 2 b levels and some state-of-the-art work [14] can achieve 2 b =128).”
BackgroundA Reconfigurable FIR Filter with Memristor-Based WeightsPreprint
Merrikh-Bayat, F., Alibart, F., Gao, L., & Strukov, D. B. (2016) · arXiv (Cornell University) · doi:10.48550/arxiv.1608.05445 · Cited by 14
Self-citationDynamics of percolative breakdown mechanism in tantalum oxide resistive switching
Lohn, A. J., Mickel, P. R., & Marinella, M. J. (2013) · Applied Physics Letters · doi:10.1063/1.4826277 · Cited by 13
Memristor panic — A survey of different device models in crossbar architectures
Woods, W., Taha, M. M. A., Tran, S. J. D., Bürger, J., & Teuscher, C. (2015) · IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) · doi:10.1109/nanoarch.2015.7180595 · Cited by 13
“find that they can reach a target state within 1% [21].”
BackgroundBuilding memristive and radiation hardness TiO2-based junctions
Ghenzi, N., Rubi, D., Mangano, E., Giménez, G., Lell, J., Zelcer, A., Stoliar, P., & Lévy, P. (2013) · Thin Solid Films · doi:10.1016/j.tsf.2013.11.013 · Cited by 13
A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory
Ghofrani, A., Lastras-Montaño, M. Á., Gaba, S., Payvand, M., Lu, W. D., Theogarajan, L. S., & Cheng, K.-T. T. (2015) · ACM Journal on Emerging Technologies in Computing Systems · doi:10.1145/2717313 · Cited by 13
A low-power hybrid reconfigurable architecture for resistive random-access memories
Lastras-Montaño, M. Á., Ghofrani, A., & Cheng, K.-T. T. (2016) · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2016.7446057 · Cited by 13
“Their solution is orthogonal to ours and can in fact be incorporated into our system if we also exploit the multilevel characteristics of the memristors for storing multiple bits per memristor [13].”
BackgroundTraining low bitwidth convolutional neural network on RRAM
Cai, Y., Tang, T., Xia, L., Cheng, M., Zhu, Z., Wang, Y., & Yang, H. (2018) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.5555/3201607.3201632 · Cited by 13
Design of resistive random access memory cell and its architecture
Dubey, S. K., & Islam, A. (2019) · Microsystem Technologies · doi:10.1007/s00542-019-04663-1 · Cited by 13
Water-based resistive switches for neuromorphic long-range connections
Ananthakrishnan, A., Du, X., & Allen, M. G. (2021) · Journal of Physics D Applied Physics · doi:10.1088/1361-6463/abead7 · Cited by 13
Programmable discrete-time type I and type II FIR filter design on the memristor crossbar structure
Mirebrahimi, S., & Merrikh‐Bayat, F. (2014) · Analog Integrated Circuits and Signal Processing · doi:10.1007/s10470-014-0275-3 · Cited by 13
Utilizing NDR effect to reduce switching threshold variations in memristive devices
Alibart, F., & Strukov, D. B. (2013) · Applied Physics A · doi:10.1007/s00339-013-7550-5 · Cited by 13
Self-citationMemristor based BPSK and QPSK demodulators with nonlinear dopant drift model
Elashkar, N. E., Aboudina, M. M., Fahmy, H. A. H., Ibrahim, G. H., & Khalil, A. H. (2016) · Microelectronics Journal · doi:10.1016/j.mejo.2016.07.015 · Cited by 13
“The only external circuit that is needed is a memristance initialization circuit as proposed in [28,29].”
Background3D ReRAM arrays and crossbars: Fabrication, characterization and applications
Adam, G. C., Chrakrabarti, B., Nili, H., Hoskins, B. D., Lastras-Montaño, M. Á., Madhavan, A., Payvand, M., Ghofrani, A., Cheng, K.-T. T., Theogarajan, L. S., et al. (2017) · IEEE International Conference on Nanotechnology (IEEE-NANO) · doi:10.1109/nano.2017.8117387 · Cited by 13
Self-citationTutorial: Fabrication and three-dimensional integration of nanoscale memristive devices and arrays
Lin, P., & Xia, Q. (2018) · Journal of Applied Physics · doi:10.1063/1.5038109 · Cited by 14
Memristor Synapses for Neuromorphic Computing
Choi, S., Ham, S., & Wang, G. (2019) · IntechOpen eBooks · doi:10.5772/intechopen.85301 · Cited by 13
An Agile Precision-Tunable CNN Accelerator based on ReRAM
He, Y., Wang, Y., Wang, Y., Li, H., & Li, X. (2019) · doi:10.1109/iccad45719.2019.8942163 · Cited by 13
“Because MLC with high storage density cells [22] are suffering from data reliability issue, large ADC power and area overhead, many researchers prefer using multiple stable SLC ReRAM cells to store one weight instead of 8 or 16 bits per cell.”
BackgroundKim, S., & Park, B. (2016) · Journal of Physics D Applied Physics · doi:10.1088/1361-6463/50/2/02lt01 · Cited by 12
Reliability Enhancements in Memristive Neural Network Architectures
Gnawali, K. P., Paudel, B. R., Mozaffari, S. N., & Tragoudas, S. (2019) · IEEE Transactions on Nanotechnology · doi:10.1109/tnano.2019.2933806 · Cited by 12
“During the first cycle, all cells in the spare column are programmed sequentially using [31], [35] to the same weight values as in the”
BackgroundMethodInfluentialHighly Parallel Writing Strategy Based on Diagonal-Gates-Connection 1T1R Arrays
Tong, P., Wang, W., Xu, H., Sun, Y. K., Wang, Y., Liu, S., Zhang, Y., Liao, C., Chen, C., & Li, Q. (2022) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2022.3214794 · Cited by 12
“1(a), accurate multivalued modulation (single pulse modulation [8], [9], variable pulse amplitude modulation [10], [12], [13] and variable pulsewidth modulation [12], [13]) can only be performed device by device because it is interfered by the devices on the same WL.”
BackgroundReBNN: in-situ acceleration of binarized neural networks in ReRAM using complementary resistive cell
Song, L., Wu, Y., Qian, X., Li, H. H., & Chen, Y. (2019) · CCF Transactions on High Performance Computing · doi:10.1007/s42514-019-00014-8 · Cited by 12
“Complex iterative tuning schemes (Alibart et al. 2012) or conversion algorithm (Hu et al. 2016) must be used.”
MethodTemporal State Machines: Using Temporal Memory to Stitch Time-based Graph Computations
Madhavan, A., Daniels, M. W., & Stiles, M. D. (2021) · ACM Journal on Emerging Technologies in Computing Systems · doi:10.1145/3451214 · Cited by 12
Yamaguchi, K., Takeuchi, S., Tohei, T., Ikarashi, N., & Sakai, A. (2018) · Japanese Journal of Applied Physics · doi:10.7567/jjap.57.06kb02 · Cited by 12
Storing and Retrieving Wavefronts with Resistive Temporal Memory
Madhavan, A., & Stiles, M. D. (2020) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas45731.2020.9180662 · Cited by 12
In‐Memory Binary Vector–Matrix Multiplication Based on Complementary Resistive Switches
Ziegler, T., Waser, R., Wouters, D. J., & Menzel, S. (2020) · Advanced Intelligent Systems · doi:10.1002/aisy.202000134 · Cited by 12
Metadata
- Authors
- Alibart, F., Gao, L., Hoskins, B. D., & Strukov, D. B.
- Affiliations
- University of California, Santa Barbara (US)
- Venue
- Nanotechnology
- Publisher
- IOP Publishing
- Published
- 2012-01-20
- Volume
- 23
- Issue
- 7
- Pages
- 075201
- ISSN
- 0957-4484 (ISSN-L)
- 1361-6528
- OpenAlex
- W2091777687
- Cited by
- 557
- References
- 35
- Citations by year
- 2026: 9 · 2025: 26 · 2024: 21 · 2023: 37 · 2022: 37 · 2021: 45 · 2020: 56 · 2019: 73 · 2018: 58 · 2017: 43 · 2016: 47 · 2015: 39 · 2014: 27 · 2013: 22 · 2012: 16
- FWCI
- 21.27
- Type
- journal article
- Language
- en
- Open access
- bronze
- doi.org
- Locations
- Nanotechnology (publishedVersion)
- PubMed (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- arXiv (Cornell University)
- Funders
- National Science Foundation (1028336, 1121053)
- Division of Materials Research (DMR 1121053, 1121053)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Keywords
- memristors, TiO2 thin films, resistive switching, conductance tuning, variation tolerance, filamentary switching, non-volatile memory, analog computing, dot product computation, summing amplifier
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
