Cited by 368Advancements in Semiconductor Devices and Circuit DesignLow-power high-performance VLSI design2D Materials and Applications

The DOI matches its Crossref record; 0 of the 13 references it cites were found in a registry or an index.

3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications

Bae, Geumjong, Bae, D.-I., Kang, M., Hwang, S.M., Kim, S.S., Seo, B., Kwon, T.Y., Lee, T.J., Moon, C., Choi, Y.M., Oikawa, K., Masuoka, S., Chun, K.Y., Park, S.H., Shin, H.J., Kim, J.C., Bhuwalka, K.K., Kim, D.H., Kim, W.J., Yoo, J., Jeon, H.Y., Yang, M.S., Chung, S.-J., Kim, D., Ham, B.H., Park, K.J., Kim, W.D., Park, S.H., Song, G., Kim, Y.H., Kang, M.S., Hwang, K.H., Park, C.-H., Lee, J.-H., Kim, D.-W., Jung, S-M., Kang, H.K.·2018·2018 IEEE International Electron Devices Meeting (IEDM)

DOI 10.1109/iedm.2018.8614629

Open this paper in CoChat — free account

Abstract

As the most feasible solution beyond FinFET technology, a gate-all-around Multi-Bridge-Channel MOSFET (MBCFET) technology is successfully demonstrated including a fully working high density SRAM. MBCFETs are fabricated using 90% or more of FinFET processes with only a few revised masks, allowing easy migration from FinFET process. Not only on-target but also multiple Vt is achieved in challengingly limited vertical spacing between channels. Also, reliability of MBCFETs is shown to be comparable to that of FinFETs. Three representative superior characteristics of MBCFET compared to FinFET have been demonstrated — better gate control with 65 mV/dec sub-threshold swing (SS) at short gate length, higher DC performance with a larger effective channel width (Weff) at reference footprint, and design flexibility with variable nanosheet (NS) widths. The optimization of the standard cell design by using variable NS width is evaluated. The usefulness of MBCFET as a multi-purpose performance provider is proven by the modulation of effective capacitance (Ceff), effective resistance (Reff) and frequency by Weff control. Finally, mass production feasibility with MBCFET is proven through a fully working high density SRAM circuit.

Integrity signals

Registry

Crossref · 10.1109/iedm.2018.8614629

Cites

0 of 13 references verified0 citation errors · 13 not checkable

Statistics

Recomputing p-values needs the paper’s full text.

Claims the paper makes

This paper’s full text isn’t openly available, so its claims and self-check weren’t run. The registry and citation checks still apply.

Claims other papers make about this one

Each is checked against this paper’s own text: does it say what the citing paper says it does?

Untitled work
mertens (2016) · IEDM
Unresolved
Untitled work
sun (2007) · Journal of Appllied Physics
Unresolved
Untitled work
kim (2015) · SOI-3D-Subthreshold Microelectrics
Unresolved
Untitled work
barraud (2017) · IEDM
Unresolved
Untitled work
lee (2003) · Trans Nanotechnol
Unresolved
Untitled work
jeong (2018) · Symposium on VLSI
Unresolved
Untitled work
kim (2006) · Symposium on VLSI
Unresolved
Untitled work
lee (2005) · Symposium on VLSI
Unresolved
Untitled work
mertens (2017) · IEDM
Unresolved
Untitled work
loubet (2017) · Symposium on VLSI
Unresolved

Flagged first, then by citations

Show all 13 references

13 of the 13 references couldn’t be matched to a known paper.

Sorted by citations

Items 101–200 of 316

Wafer-scale uniform epitaxy of transferable 2D single crystals for gate-all-around nanosheet field effect transistors
Xue, C., Tan, C., Gao, X., Tang, J., Sun, W., Yin, Y., Wang, M., Gao, X., An, H., Fu, B., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-65641-y · Cited by 10
“Since only oxygen stable metal could be used as the contact, will it sacrifice the contact resistance of final transistors, please compare with previous study in terms of on-state current.”
Loading Effect during SiGe/Si Stack Selective Isotropic Etching for Gate-All-Around Transistors
Shao, H., Reiter, T., Chen, R., et al. (2024) · ACS Applied Electronic Materials · doi:10.1021/acsaelm.4c01462 · Cited by 9
Enhancing Gate Control and Mitigating Short Channel Effects in 20–50 nm Channel Length Amorphous Oxide Thin-Film Transistors
Yoon, C., Ahn, J., Zhou, Y., et al. (2025) · ACS Nano · doi:10.1021/acsnano.5c10260 · Cited by 9
Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs
Jeong, J., Yoon, J.-S., & Baek, R. (2021) · IEEE Access · doi:10.1109/access.2021.3053572 · Cited by 10
“Meanwhile, multi-stacked silicon gate-all-around (GAA) nanosheet FETs (NSFETs) demonstrate superior gate electrostatics, larger W eff per foot-print, and higher drive current than FinFETs below the 7-nm node [7], [9], [10].”
Background
Device Design and Reliability of GAA MBCFET
Kang, M., Chang, M., Park, Y., et al. (2024) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps48228.2024.10529401 · Cited by 8
“[ 12], [16] B.”
BackgroundSelf-citation
Optimal Transistor Folding and Placement for Synthesizing Standard Cells of Complementary FET Technology
Kim, S., & Kim, T. (2024) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1145/3649329.3658261 · Cited by 10
Self-citation
Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height
Gaddemane, G., Schuddinck, P., Bhuwalka, K. K., et al. (2024) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2024.3498092 · Cited by 9
“1a) emerges as a promising solution, enabling aggressive scaling of the contacted gate pitch (CGP) and offering a substantial drive current per footprint advantage [1] [2].”
Self-citation
Enabling the Angstrom Era: 2D material-based multi-bridge-channel complementary field effect transistors
Yoon, H. H., Park, J. Y., Megra, Y. T., et al. (2025) · npj 2D Materials and Applications · doi:10.1038/s41699-025-00591-z · Cited by 8
Self-citation
Middle-of-the-Line Reliability Characterization of Recessed-Diffusion-Contact Adopted sub-5nm Logic Technology
Kim, S., Jung, U., Choo, S., et al. (2022) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps48227.2022.9764599 · Cited by 8
“Stacked nanosheet transistors, multibridge-channel MOSFETs, and gate-all-around (GAA) transistors have been also introduced for low power and high-performance application by increasing channel width [7-13].”
BackgroundSelf-citation
Attoampere Level Leakage Current in Chemical Vapor Deposition-Grown Monolayer MoS2 Dynamic Random-Access Memory in Trap-Assisted Tunneling Limit
Seok, J., Seo, J. E., Lee, D. K., et al. (2025) · ACS Nano · doi:10.1021/acsnano.4c13376 · Cited by 8
Vertical heterojunction Ge0.92Sn0.08/Ge gate-all-around nanowire pMOSFETs with NiGeSn contact
Liu, M., Mertens, K., von den Driesch, N., et al. (2019) · Solid-State Electronics · doi:10.1016/j.sse.2019.107716 · Cited by 8
“Among those, GAA nanowire transistors have gained numerous interest due to superior gate electrostatic control and low leakage currents for ultra-scaled sub-10 nm technology nodes [1-3].”
Background
DTCO of Nanosheet and Forksheet Architectures: Exploring Dielectric Walls, Contacting Schemes, and Active Regions for Optimized RO Performance
Gaddemane, G., Schuddinck, P., Bhuwalka, K. K., et al. (2024) · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · doi:10.1109/edtm58488.2024.10511609 · Cited by 8
“1a) allows aggressive contacted poly pitch (CPP) scaling as well as delivering substantial drive current per footprint advantage [1], [2].”
BackgroundSelf-citation
Automatic Modeling of Logic Device Performance Based on Machine Learning and Explainable AI
Kim, S., Lee, K., Noh, H.-K., Shin, Y., Chang, K.-B., Jeong, J. H., Baek, S., Kang, M., Cho, K. H., Kim, D.-W., et al. (2020) · International Conference on Simulation of Semiconductor Processes and Devices · doi:10.23919/sispad49475.2020.9241681 · Cited by 9
Self-citation
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks
Rawat, A., Bhuwalka, K. K., Matagne, P., et al. (2021) · European Solid-State Device Research Conference · doi:10.1109/essderc53440.2021.9631815 · Cited by 7
Self-citation
Research Progresses on Suppressing the Short-Channel Effects of Field-Effect Transistor
Huang, J. (2022) · Highlights in Science Engineering and Technology · doi:10.54097/hset.v27i.3779 · Cited by 7
“Samsung presented 3 nm MBCFET based on GAA technology with three superior characteristics compared to FinFET—better gate control, higher performance with larger Weff and more flexible design with variable nanosheet widths [6].”
Method
Growth and characterization of SiGe/Si superlattice for vertically stacked DRAM
Wang, H., Wang, X., Song, Y., et al. (2025) · Journal of Materials Science Materials in Electronics · doi:10.1007/s10854-024-14167-y · Cited by 8
Dipole engineering at HfO2/SiO2 interface by ultra-thin Al2O3 to modulate flat-band voltage for cryogenic temperatures
Huang, Z., Liu, T., Qian, L., et al. (2025) · Vacuum · doi:10.1016/j.vacuum.2025.114073 · Cited by 7
BSIM-CMG Compact Model for IC CAD: from FinFET to Gate-All-Around FET Technology
Dasgupta, A., & Hu, C. C. (2020) · Journal of Microelectronic Manufacturing · doi:10.33079/jomm.20030402 · Cited by 7
Significance of Overdrive Voltage in the Analysis of Short-Channel Behaviors of n-FinFET Devices
Eng, Y.-C., Hu, L., Chang, T.-F., et al. (2022) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2022.3160881 · Cited by 7
Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation
An, D. G., Kim, G., Kim, H., et al. (2023) · Semiconductor Science and Technology · doi:10.1088/1361-6641/ad10c4 · Cited by 7
Self-citation
Epitaxially Stacked 12‐Layer Perovskite Oxide Heterostructure as a Double‐Level Double‐Gate Field‐Effect Transistor
Kim, J., Seo, J., Lee, H., et al. (2024) · Advanced Functional Materials · doi:10.1002/adfm.202402059 · Cited by 7
Self-citation
Rigorous Modeling and Investigation of Low-Field Hole Mobility in Silicon and Germanium Gate-All-Around Nanosheet Transistors
Zhang, S., Xie, H., Huang, J. Z., et al. (2022) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2022.3188231 · Cited by 7
“In addition, some other benefits have also been shown by many studies up to date, including more design/fabrication flexibility [3], area efficiency [4], and integration density [5].”
Background
Simulation Study: The Impact of Structural Variations on the Characteristics of a Buried-Channel-Array Transistor (BCAT) in DRAM
Sun, M., Baac, H. W., & Shin, C. (2022) · Micromachines · doi:10.3390/mi13091476 · Cited by 7
Short channels and mobility control of GAA multi stacked nanosheets through the perfect removal of SiGe and post treatment
Bae, D., & Choi, B. ‐. (2020) · Electronics Letters · doi:10.1049/el.2019.3459 · Cited by 7
Self-citation
Optimization of zero-level interlayer dielectric materials for gate-all-around silicon nanowire channel fabrication in a replacement metal gate process
Zhang, Q., Tu, H., Zhang, Z., et al. (2020) · Materials Science in Semiconductor Processing · doi:10.1016/j.mssp.2020.105434 · Cited by 7
Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage
Yoo, C., Chang, J., Park, S., et al. (2022) · Nanomaterials · doi:10.3390/nano12040591 · Cited by 7
Self-citation
Stacked gate-all-around nanosheet transistors with full-air-spacers for reducing parasitic capacitance to improve device and circuit performance
Li, L., Cao, L., Zhang, X., et al. (2024) · Microelectronics Journal · doi:10.1016/j.mejo.2024.106535 · Cited by 6
Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering
Zhang, X., Li, Q., Cao, L., et al. (2025) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2025.3531432 · Cited by 6
“A series of design optimization technologies for NSFETs building standard 6T-SRAM cells are reported [14], [15], [16], [17].”
Nanosheet Transistors Produced in 300 mm Fabrication Platform for Quantum Computing
Rohrbacher, C., Leclerc, D., Rivard, J., Ritzenthaler, R., Lupien, C., Mertens, H. W., Horiguchi, N., & Dupont-Ferrier, E. (2025) · IEEE Electron Device Letters · doi:10.1109/led.2025.3556348 · Cited by 6
“But the semiconductor industry is still evolving with the next generation of nanosheet transistors aimed to go beyond the current FinFET technology [19].”
Highly Selective Isotropic Etching of Si to SiGe Using CF4/O2/N2 Plasma for Advanced GAA Nanosheet Transistor
Li, J., Sun, X., Huang, Z., et al. (2025) · Nanomaterials · doi:10.3390/nano15191469 · Cited by 6
Nanosheet-based complementary transistors with a 48 nm pitch
Wang, Y. (2023) · Nature Electronics · doi:10.1038/s41928-023-01090-z · Cited by 6
Scaling of N-Type Field-Effect Transistors Based on Aligned Carbon Nanotube Arrays
Liu, C., Cao, Y., Lu, H., et al. (2024) · ACS Applied Materials & Interfaces · doi:10.1021/acsami.4c11320 · Cited by 6
Ultraflat hexagonal boron nitride for high-κ dielectric integration
Ko, H., Lee, S., & Kim, K. K. (2024) · Nature Materials · doi:10.1038/s41563-024-02013-9 · Cited by 6
Switched-Capacitor-Assisted Power Gating for Ultra-Low Standby Power in CMOS Digital ICs
Sankar, S., Goel, M., Chen, P.-H., et al. (2020) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2020.3015430 · Cited by 6
Work-Function Variability impact on the performance of Vertically Stacked GAA FETs for sub-7nm Technology Node
Mohapatra, E., Jena, D., Das, S., et al. (2022) · IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON) · doi:10.1109/edkcon56221.2022.10032850 · Cited by 6
High-fidelity moulding growth and cross-section shaping of ultrathin monocrystalline silicon nanowires
Liang, Y., Qian, W., Hu, R., Gan, X., Shi, S., Li, Y., Wang, J., Liu, Z., He, D., Shi, Y., et al. (2023) · Applied Surface Science · doi:10.1016/j.apsusc.2023.157635 · Cited by 6
Advances and Future Challenges in Monolithic 3D Integrated Logic, Power, and Optoelectronics Technologies for Tightly Interconnected Intelligent Systems
Jung, H., Choi, J., Baek, S., Shin, B. G., Song, Y. J., Jung, H., Kim, J. J., Jeon, J., Kim, G., Park, H., et al. (2026) · ACS Nano · doi:10.1021/acsnano.5c15601 · Cited by 6
Self-citation
The study of electron mobility on ultra-scaled silicon nanosheet FET
Liu, T., Rezaei, A., Yang, K., et al. (2024) · Physica Scripta · doi:10.1088/1402-4896/ad56d9 · Cited by 5
Source/drain extension asymmetric counter-doping for suppressing channel leakage in stacked nanosheet transistors
Li, Q., Cao, L., Zhang, Q., et al. (2024) · Microelectronics Journal · doi:10.1016/j.mejo.2024.106347 · Cited by 5
Nanowire-Based Si-CMOS Devices
Mishra, R. K., Mishra, V., & Mishra, S. N. (2024) · Springer tracts in electrical and electronics engineering · doi:10.1007/978-981-97-4623-1_2 · Cited by 5
W-Shaped Silicon Channels to Increase the Channel Perimeter and Improve the Output Current of Multi-Bridge-Channel FETs
Lee, M.-K., Park, H., Kil, T.-H., et al. (2025) · Silicon · doi:10.1007/s12633-025-03243-5 · Cited by 5
Analysis of electron mobility in 7-level stacked nanosheet GAA nMOSFETs
de Souza, M. S., Rodrigues, J. C., da Silva, L. M. B., et al. (2025) · Solid-State Electronics · doi:10.1016/j.sse.2025.109115 · Cited by 5
Experimenting with Beta Distributions for Approximating Hammocks’ Reliability
Cowell, S. R., Hoară, S., & Beiu, V. C. (2020) · Advances in intelligent systems and computing · doi:10.1007/978-3-030-53651-0_6 · Cited by 5
Scavenger with Protonated Phosphite Ions for Incredible Nanoscale ZrO2-Abrasive Dispersant Stability Enhancement and Related Tungsten-Film Surface Chemical–Mechanical Planarization
Kim, S.-I., Jeong, G.-P., Lee, S., et al. (2021) · Nanomaterials · doi:10.3390/nano11123296 · Cited by 5
Self-citation
Surface Transformation of Spin-on-Carbon Film via Forming Carbon Iron Complex for Remarkably Enhanced Polishing Rate
Lee, J.-M., Lee, J., Kim, S.-I., et al. (2022) · Nanomaterials · doi:10.3390/nano12060969 · Cited by 5
Self-citation
Investigation of SiGe/Si Bilayer Inverted-T Channel Gate-All-Around Field-Effect-Transistor With Self-Induced Ferroelectric Ge Doped HfO₂
Sun, C.-J., Yao, Y.-J., Yan, S.-C., et al. (2022) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2022.3179465 · Cited by 5
Improved Monolayer MoS Performance With Two-Step Atomic Layer Deposited High- Dielectrics
Chou, B.-J., Chang, Y., Chang, W., et al. (2022) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2022.3223228 · Cited by 5
“silicon field-effect transistor (FET) scaling, however, fin scaling of Si-based transistors encounters great difficulty due to stronger surface scattering as the fin width goes thinner than 4 nm [1], [2], [3].”
Background
Literature Review of Energy Consumption Modeling for Mobile Devices
Outmani, A. E., Jaara, E. M., & Azizi, M. (2023) · Lecture notes in networks and systems · doi:10.1007/978-3-031-35245-4_9 · Cited by 5
Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures
de Souza, M. S., Cerdeira, A., Estrada, M., et al. (2023) · Solid-State Electronics · doi:10.1016/j.sse.2023.108716 · Cited by 5
Design and temperature analysis of tree-shaped nanosheet FET for analog and RF applications
Gowthami, U., Prakash, M. D., Patta, S., et al. (2024) · Physica Scripta · doi:10.1088/1402-4896/ad9cf8 · Cited by 6
Analysis of n & p-channel heterojunction nanosheet MOSFET for logic circuit
Tripathi, S. L., Prakash, N. N., & Wijayanto, I. (2025) · Discover Applied Sciences · doi:10.1007/s42452-025-07683-x · Cited by 5
“…and p-channel devices within the same nanosheet platform enables evaluation of critical parameters such as threshold voltage (V th ), transconductance (g m ), subthreshold swing (SS) and I on /I off ratios, offering deeper insight into device symmetry and complementary logic compatibility [20].”
A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs
Lee, S., Jeong, J., Kang, B., et al. (2023) · Nanomaterials · doi:10.3390/nano13050868 · Cited by 5
Self-citation
Defect spectroscopy of sidewall interfaces in gate-all-around silicon nanosheet FET
Lee, K., Kim, Y., Lee, H., et al. (2020) · Nanotechnology · doi:10.1088/1361-6528/abd278 · Cited by 5
Self-citation
Optimizing analog performance: the advantage of vertical MBCFETs in linearity and footprint
Saha, R., Prasad, R., Singh, U. P., & Maity, S. K. (2025) · Engineering Research Express · doi:10.1088/2631-8695/adf413 · Cited by 4
A novel thermal network model and electro-thermal coupling study for NSFETs and CFETs considering thermal crosstalk
Miao, T., Zheng, Q., Hu, Y., Cheng, X., Liang, J., Chen, L., Guo, A., Liu, J., Ren, K., & Zhang, J. (2025) · Micro and Nanostructures · doi:10.1016/j.micrna.2025.208322 · Cited by 5
Plasma Etching of Multilayer SiO 2 /Si 3 N 4 Alternating Stacks Using Capacitively Coupled Plasma‐Reactive Ion Etching
Guo, J., Fan, Y., Huang, H., Wang, Y., Zhang, Y., Chen, Z., Zhang, J., Yu, L., & Ye, S. (2026) · physica status solidi (a) · doi:10.1002/pssa.202500820 · Cited by 5
Reliability challenges in Forksheet Devices: (Invited Paper)
Bury, E., Vandemaele, M., Franco, J., et al. (2023) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps48203.2023.10118269 · Cited by 4
“INTRODUCTION As ultimate gate-all-around FETs, nanosheets are on the verge of being implemented in contemporary VLSI technologies [1,2], due to their enhanced channel control and stacking potential [3,4].”
Background
Etching Technologies in Semiconductor Manufacturing: A Short Review
Mahtab, S. S., Anonto, R. A., Talukder, T., et al. (2025) · Advances in Science, Technology & Innovation/Advances in science, technology & innovation · doi:10.1007/978-3-031-73816-6_36 · Cited by 4
Device Design Guidelines to Boost Up AC Performance of CFET (Complementary Field-Effect-Transistor)-Based Inverter
Lim, J., Han, D., Sung, J., et al. (2025) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2025.3539599 · Cited by 4
“D transistor architectures (FinFETs) at the 22 nm node [3], and state-of-the-art transistor structures (GAAFETs) at the 3 nm node [4].”
Performance improvement of gate-all-around (GAA) devices by optimized super-steep retrograde well
Li, Q., Zhang, Q., Cao, L., et al. (2025) · Microelectronics Journal · doi:10.1016/j.mejo.2025.106723 · Cited by 4
A Comprehensive Analysis of Nanosheet Field-Effect Transistor: Recent Advances and Comparative Study
Chauhan, A. S., & Raman, A. (2024) · NANO · doi:10.1142/s1793292024500590 · Cited by 4
Intrinsic performance limits of extremely scaled field-effect transistors based on MX2 (M = {Zr, Hf}, X = {S, Se}) nanoribbons
Matić, M., & Poljak, M. (2024) · Journal of Applied Physics · doi:10.1063/5.0224088 · Cited by 4
Design Decoupling of Inner- and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling
Bhuwalka, K. K., Baumgartner, O., Wu, H., et al. (2024) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2024.3492722 · Cited by 5
“As gate-all-around (GAA) nanosheet (NS) MOSFETs enter production stage [1], [2], [3], [4], [5], [6], [7], [8], [9], an important aspect to consider is multi-node scalability.”
Self-citation
Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology
Liu, Y., Yin, M., Zhou, H., et al. (2025) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2025.3529504 · Cited by 4
First Principle and NEGF Based Study of Silicon Nano-wire and Nano-sheet for Next Generation FETs: Performance, Interface Effects and Lifetime
Sikder, O., & Schubert, P. J. (2020) · IEEE International Conference on Nanotechnology (IEEE-NANO) · doi:10.1109/nano47656.2020.9183675 · Cited by 4
“1(ab)) and Multi-Bridge-Channel (MBC)-FETs[6] (Fig.”
Strain effect on performance of multi-stacked gate-all-around CMOS inverters
Kim, K., Lee, J. H., & Oh, S. (2020) · Semiconductor Science and Technology · doi:10.1088/1361-6641/abbc8e · Cited by 4
Self-citation
DC and Analog/RF Performance Analysis of Multi-Bridge Channel FET with Variation in Gate Work Function
Yadav, N., Jadav, S., & Saini, G. (2022) · International Conference for Advancement in Technology (ICONAT) · doi:10.1109/iconat53423.2022.9726102 · Cited by 4
Retraction: A survey on the latest FET technology for samsung industry
ALRikabi, H. T. S., & Ali, G. M. (2023) · AIP conference proceedings · doi:10.1063/5.0181953 · Cited by 4
Retracted
Performance Analysis of Nanosheet Transistors for Analog ICs
Pundir, Y. P., Bisht, A., & Pal, P. K. (2024) · doi:10.1002/9781394188970.ch11 · Cited by 4
Extrapolation of Metal Gate With High-K Spacer in Strained Nanosystem Channel QWB Cylindrical FET for High-Speed Applications
Barik, R., Dhar, R. S., Kumar, K., et al. (2025) · IEEE Access · doi:10.1109/access.2025.3534561 · Cited by 3
Stress-Aware Performance Optimization in Gate-All-Around NSFET and Beyond
Teng, F., Yan, X., Jin, J., et al. (2025) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2025.3569503 · Cited by 3
“We also calibrated the transfer characteristics of both pFET and nFET refer to the silicon data from [20].”
Junction Depth Optimization in Trench Gate Nanosheet FETs for Reduced Off-State Current
Bang, D.-E., Lee, M.-K., Yun, E.-C., et al. (2025) · Silicon · doi:10.1007/s12633-025-03439-9 · Cited by 3
Compact modeling of 2D nanotransistors: materials characteristics, device structures, and analytical techniques
de Souza, A. M., Celino, D. R., Ragi, R., et al. (2025) · Nanotechnology · doi:10.1088/1361-6528/ae00ce · Cited by 3
Evolution and Analysis of GaN GAA FET Induced High-K Spacer Wrapped Gate Underlap for Superfast Circuitry and RF Applications
Singh, S., Devi, P., Dhar, R. S., et al. (2025) · IEEE Access · doi:10.1109/access.2025.3608819 · Cited by 3
“Among these, device O 7 exhibits the highest switching speed outperforming the newly developed devices C, C 7 , I, I 7 and O as well as the existing devices IRDS 2028 [21], S (Samal et al. [26]), T (Wang et al. [27]), U (Panigrahy et al. [28]) and Z (Son et al. [25]) configurations.”
Scaling Options for GAA Nanosheet Based Devices: Role of Decoupling Inner- and Outer-Gate Lengths
Bhuwalka, K. K., Baumgartner, O., Wu, H., et al. (2024) · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · doi:10.1109/edtm58488.2024.10511534 · Cited by 3
Self-citation
Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node
Jeong, J. H., Shin, Y., Lee, H., et al. (2024) · IEEE Access · doi:10.1109/access.2024.3427332 · Cited by 3
“…(FinFET, Nanosheet FET) have solved the planar-MOSFET technology scaling limitations such as short-channel effect and leakage power [1], [2], [3], [4], and new process technologies such as double-patterning and EUV technology have overcome the challenges of interconnect scaling which,…”
BackgroundSelf-citation
A novel nanoscale FD-SOI MOSFET with energy barrier and heat-sink engineering for enhanced electric field uniformity
Anvarifard, M. K., & Ramezani, Z. (2024) · Micro and Nanostructures · doi:10.1016/j.micrna.2024.207986 · Cited by 3
QUDEN : A Matlab Package for First‐Principles Quantum‐Transport Engineering of 2D Material‐Based Nanodevices
Matić, M., & Poljak, M. (2025) · International Journal of Numerical Modelling Electronic Networks Devices and Fields · doi:10.1002/jnm.70079 · Cited by 3
Enhancing DM Junctionless Tree-FET Performance Through Spacer Optimization: A Comprehensive DC and RF Analysis
Beebireddy, D., Fatima, K., & Devi, L. N. (2025) · Journal of Electronic Materials · doi:10.1007/s11664-025-11761-6 · Cited by 3
“11–13 GAA FETs, which include nanowire (NW) and nanosheet (NS) architectures, offer superior gate control by surrounding the channel from all sides, resulting in a higher ON/OFF-current ratio.”
Variability-Aware DTCO Flow: Projections to N3 FinFET and Nanosheet 6T SRAM
Karner, M., Rzepa, G., Baumgartner, O., et al. (2021) · International Conference on Simulation of Semiconductor Processes and Devices · doi:10.1109/sispad54002.2021.9592527 · Cited by 3
Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs
Xu, B., Wang, G., Du, Y., et al. (2022) · Nanomaterials · doi:10.3390/nano12091403 · Cited by 3
A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node
Jeong, J. H., Ko, J., & Song, T. (2022) · ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) · doi:10.1145/3531437.3539707 · Cited by 3
“Modern semiconductor designers have tried to improve chip power, performance, and area (PPA) by achieving transistor node scaling and developing new device structures such as Gate-All-Around FET (GAAFET) and FinFET [1, 2, 9].”
BackgroundInfluential
Second harmonic generation and simplified bond hyperpolarizability model analyses on the intermixing of Si/SiGe stacked multilayers for gate-all-around structure
Chen, W.-T., Yen, T.-Y., Hung, Y.-H., et al. (2023) · Nanotechnology · doi:10.1088/1361-6528/acb1b5 · Cited by 3
“Horizontal gate-all-around ( GAA ) devices will be the suc-ceeding ﬁ n ﬁ eld-effect transistor technology for next-generation logic architecture [ 1, 2 ] .”
Reliability of Multiple-Layer Stacked Gate-All-Around Poly-Si Nanosheet Channel Ferroelectric HfxZr1-xO2FETs With NH3 Plasma Treatment
Hsieh, D., Lee, C., Hong, T.-C., et al. (2023) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2023.3274610 · Cited by 3
Soft-Error Sensitivity in SRAM Manufactured by Bulk Gate-All-Around (GAA) Technology
Uemura, T., Chung, B., Choi, J., et al. (2024) · IEEE International Reliability Physics Symposium proceedings · doi:10.1109/irps48228.2024.10529300 · Cited by 3
“After bulk-planar, FDSOI-planar, and bulk-FinFET technologies, bulk gate-all-around (bulk-GAA) technology has been developed to achieve more performance [2].”
MethodSelf-citation
Study of Inner Spacer Module Process for Gate All Around Field Effect Transistors
Yang, C., Li, J., Liu, E., et al. (2024) · ECS Journal of Solid State Science and Technology · doi:10.1149/2162-8777/ad670c · Cited by 3
CMOS Technology Compatible Magnetic Memories
Sverdlov, V. A., & Selberherr, S. (2019) · International Symposium on Next-Generation Electronics · doi:10.1109/isne.2019.8896421 · Cited by 3
“While semiconductor chips based on the 5nm technology node are approaching production, the research is shifting towards the 3nm technology node [1].”
Method
Dislocation sink annihilating threading dislocations in strain-relaxed Si 1− x Ge x layer
Choi, S.-J., Kim, I. H., Jun-Seong, P., et al. (2019) · Nanotechnology · doi:10.1088/1361-6528/ab58ab · Cited by 3
Advanced CMOS Integration Technologies for Future Mobile Applications
Claeys, C. L., & Simoen, E. R. (2019) · Symposium on Microelectronics Technology and Devices · doi:10.1109/sbmicro.2019.8919478 · Cited by 3
Metalearning Based Adaptive Compact Modeling Framework for Advanced Transistors Across Technology Nodes
Parandiyal, S., Kumar, A., Ehteshamuddin, M., et al. (2025) · IEEE Transactions on Artificial Intelligence · doi:10.1109/tai.2025.3557775 · Cited by 2
ChatTCAD: Leveraging Large Language Models for Automated TCAD Simulation File Generation
Zhang, Z., Nassif, S., & Tahoori, M. B. (2025) · IEEE Computer Society Annual Symposium on VLSI · doi:10.1109/isvlsi65124.2025.11130247 · Cited by 3
“For example, gate-all-around (GAA) transistor architecture enables further scaling beyond traditional planar transistors [2], while wide-bandgap materials like silicon carbide (SiC) [3] offer superior performance in high-voltage and power devices, and are also being explored in combination with…”
Design and analysis of high-k wrapped underlap induced GaN multi-channel GAA nanosheet FET for enhanced performance with cut-off frequency in THz range
Singh, S., Dhar, R. S., Banerjee, A., & Gupta, V. (2025) · Scientific Reports · doi:10.1038/s41598-025-28275-0 · Cited by 2
Chained Materials: Definition, Understandings, and Applications
Lu, S., Li, K., Wang, L., Zhou, Y., Chen, C., & Tang, J. (2026) · Chemical Reviews · doi:10.1021/acs.chemrev.5c00527 · Cited by 2
Investigation of Electro-Thermal Performance for TreeFET from the Perspective of Structure Parameters
Liu, W., Pan, X., Liu, J., et al. (2023) · Electronics · doi:10.3390/electronics12071529 · Cited by 4
Low-Temperature Effects on Electron Transport in Small-Diameter Silicon Nanowire
Verma, A., Shiri, D., & Nekovei, R. (2023) · IEEE Nanotechnology Materials and Devices Conference (NMDC) · doi:10.1109/nmdc57951.2023.10343599 · Cited by 2
Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures
de Souza, M. S., Cerdeira, A., Estrada, M., et al. (2024) · Solid-State Electronics · doi:10.1016/j.sse.2024.108865 · Cited by 2
Multi-VT Options at Scaled Vertical Pitch in Gate-All-Around Nanosheet Devices by Independent Inner-Outer Work-function Tuning
Gaddemane, G., Bhuwalka, K. K., Rzepa, G., et al. (2024) · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · doi:10.1109/edtm58488.2024.10512044 · Cited by 2
“Gate-all-around (GAA) nanosheet (NS) transistors have been recognised as the successor for FinFET [1], [2] and are currently being implemented for the 3-nm technology node [3].”
BackgroundSelf-citation
Improved RF Performance with Buried Power Rail and Contact over Active Gate in Nanosheet FETs
Chiu, H.-C., & Hu, V. P. (2024) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas58744.2024.10558338 · Cited by 2
“Furthermore, nanosheet FETs (NSFETs), with their vertically stacked channels, have improved gate control, sub-threshold swing, and expanded effective channel width [8]- [10].”
Background
Combining quasi-one-dimensional modeling with region-wise structure analysis for rapid technology computer-aided design simulations of gate-all-around MOSFETs
Lee, K.-W., Kim, I. K., Jung, S.-W., et al. (2025) · Communications Engineering · doi:10.1038/s44172-025-00509-z · Cited by 2
Self-citation
Self-heating-aware cell design for p/n-vertically-integrated nanowire on FinFET beyond 3 nm technology node
Yamagishi, T., Hori, A., Wakabayashi, H., et al. (2020) · Japanese Journal of Applied Physics · doi:10.35848/1347-4065/ab6d83 · Cited by 2

Authors: Bae, G., Bae, D.-I., Kang, M., Hwang, S. M., Kim, S. S., Seo, B., Kwon, T. Y., Lee, T. J., Moon, C., Choi, Y. M., Oikawa, K., Masuoka, S., Chun, K. Y., Park, S. H., Shin, H. J., Kim, J. C., Bhuwalka, K. K., Kim, D. H., Kim, W. J., Yoo, J., Jeon, H. Y., Yang, M. S., Chung, S.-J., Kim, D., Ham, B. H., Park, K. J., Kim, W. D., Park, S. H., Song, G., Kim, Y. H., Kang, M. S., Hwang, K. H., Park, C.-H., Lee, J.-H., Kim, D.-W., Jung, S.-M., & Kang, H. K.
Affiliations: Samsung Electronics, Samsung R&D Center, Hwasung-City, Gyeonggi-Do, Republic of Korea
Samsung (South Korea) (KR)
ORCID: Hwang, S.M.
Seo, B.
Shin, H.J.
Bhuwalka, K.K.
Kim, D.H.
Yang, M.S.
Ham, B.H.
Kim, Y.H.
Lee, J.-H.
Kang, H.K.
Venue: 2018 IEEE International Electron Devices Meeting (IEDM)
Publisher: IEEE
Published: 2018-12
Pages: 28.7.1-28.7.4
ISSN: 0163-1918 (ISSN-L)
DOI: 10.1109/iedm.2018.8614629
OpenAlex: W2913404074
Cited by: 368
References: 13
Citations by year: 2026: 38 · 2025: 83 · 2024: 64 · 2023: 52 · 2022: 53 · 2021: 38 · 2020: 27 · 2019: 13
FWCI: 31.10
Type: conference paper
Language: en
Open access: closed
Licence: doi.org/10.15223/policy-029 (stm-asf)
doi.org/10.15223/policy-037 (stm-asf)
Locations: Technical digest - International Electron Devices Meeting/Technical digest (publishedVersion)
Topics: Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
Physical Sciences › Materials Science › Materials Chemistry › 2D Materials and Applications
Keywords: gate-all-around MOSFET, subthreshold swing, effective channel width, standard cell design, SRAM, device reliability, low power design, effective capacitance, effective resistance

About these checks

Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.

Statistics and arithmetic are recomputed, not judged.

Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.

What counts as a claim ›How we measure confidence ›How we check this ›

Are you an author, or do you see a problem with this page? Request a review

3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications

Abstract

Overview

Integrity signals

Verification

Claims the paper makes

Claims other papers make about this one

Citations

Cites

Cited by

Related

Metadata

Record

About these checks