The DOI matches its Crossref record; 0 of the 13 references it cites were found in a registry or an index.
3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications
Abstract
As the most feasible solution beyond FinFET technology, a gate-all-around Multi-Bridge-Channel MOSFET (MBCFET) technology is successfully demonstrated including a fully working high density SRAM. MBCFETs are fabricated using 90% or more of FinFET processes with only a few revised masks, allowing easy migration from FinFET process. Not only on-target but also multiple Vt is achieved in challengingly limited vertical spacing between channels. Also, reliability of MBCFETs is shown to be comparable to that of FinFETs. Three representative superior characteristics of MBCFET compared to FinFET have been demonstrated — better gate control with 65 mV/dec sub-threshold swing (SS) at short gate length, higher DC performance with a larger effective channel width (Weff) at reference footprint, and design flexibility with variable nanosheet (NS) widths. The optimization of the standard cell design by using variable NS width is evaluated. The usefulness of MBCFET as a multi-purpose performance provider is proven by the modulation of effective capacitance (Ceff), effective resistance (Reff) and frequency by Weff control. Finally, mass production feasibility with MBCFET is proven through a fully working high density SRAM circuit.
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“The lack of process margin to further scale fins, combined with parasitic effects that counteract performance increases at higher fin heights, means that finFETs have reached their limits of scaling and performance 96 .”
From Extreme ultraviolet lithography (2024) · cites this paper as [96]
In the citing paper
“This led to the introduction of gate -allaround field -effect transistor (GAAFET or nanosheet) technology in HVM, wherein the transistor channels are in stacked nanosheets with the gate wrapped around them 96 , 97 .”
From Extreme ultraviolet lithography (2024) · cites this paper as [96]
Citations
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kim (2006) · Symposium on VLSI
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mertens (2017) · IEDM
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loubet (2017) · Symposium on VLSI
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Items 301–316 of 316
Lee, H., & Shin, C. (2026) · Semiconductor Science and Technology · doi:10.1088/1361-6641/ae6df5
“…nanosheet gate-all-around (GAA) transistors, which have emerged as one of the key device architectures for advanced logic technology nodes beyond FinFET scaling owing to their superior electrostatic control, flexible effective width, and compatibility with continued cell-level scaling [4–6].”
Cryogenic performance analysis of stacked nanosheet-based GAA-MBCFETs: from 300 K to 4.3 K
Mishra, V. K., Kumar, T., Singh, A. P., et al. (2026) · Physica Scripta · doi:10.1088/1402-4896/ae7673
“By employing stacked nanosheets completely wrapped by a gate dielectric, MBCFETs provide superior electrostatic control, reduced leakage, and higher drive currents [10–14].”
Cao, S., Liu, H., Sun, L., et al. (2026) · Microelectronics Journal · doi:10.1016/j.mejo.2026.107296 · Cited by 1
Experimental Demonstration of Air Spacers in GAA CMOS for Simultaneous C eff and Delay Reduction
Jiang, R., Yang, K., Cao, L., et al. (2026) · IEEE Electron Device Letters · doi:10.1109/led.2026.3702951
“Shallow trench isolation (STI) and dummy-gate fabrication followed standard conventional GAAFET processing [20], [21], where the gate-to-LP lateral gap was precisely tuned to 30 nm per side.”
Yang, X., Zhang, H., Wang, D., et al. (2026) · Microelectronics Journal · doi:10.1016/j.mejo.2026.107337
Power Side-Channel Attacks in Nanosheet Circuits
Nabeel, M., Eddine, H. N., Benkhelifa, M., et al. (2026) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas66217.2026.11562355
“NSFET technology has emerged as the next step in the evolution of 3D transistor architectures [9], providing an excellent electrostatic control over the channel.”
Eom, S., Lee, S., Lee, J., et al. (2026) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2026.3706182
“To address these challenges, gate-all-around (GAA) nanosheet FETs (NSFETs) have emerged as the leading next-generation architecture, promising superior gate controllability, lower capacitance, and enhanced performance [12], [13], [14], [15].”
Self-citationJung, H., Lim, J., Kim, I., et al. (2026) · doi:10.1109/vlsitechnologyandcir65830.2026.11577550
Self-citationSimulation Study of Short Channel Effects in New Hemispherical Gate-All-Around (HGAA) MOS Devices
Balestra, F., & Ghibaudo, G. (2026) · Applied Sciences · doi:10.3390/app16136671
Lim, S., Lim, J., Han, D., et al. (2026) · Electronics · doi:10.3390/electronics15143004
Design and Analysis of Nanosheet FET With Asymmetric Dual- κ Inner Spacer in DC and RF Perspective
Lee, S. M., & Kim, H. (2026) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2026.3711635
“G ATE-ALL-AROUND (GAA) transistors have emerged as the state-of-the-art architecture for sub-3-nm technology nodes owing to superior electrostatic control and a larger e ff ective channel width [1], [2], [3], [4], [5].”
Wu, J., Luo, Y., Hu, J., Li, S. S., Cai, S., Cheng, T., Zhang, P., LI, P., Jiang, S., Liu, Z., et al. (2026) · Micromachines · doi:10.3390/mi17070864
On the functional significance of quantum effects at subneuronal scales
Roeloffs, J., & Tuszyński, J. A. (2026) · Biosystems · doi:10.1016/j.biosystems.2026.105905
Cheng, H., Yang, Z., Zhang, C., & Zhang, Z. (2026) · Nanomaterials · doi:10.3390/nano16171053
Design and Analysis of Gate Stack 7 nm Triple Material Gate Nanosheet FET for Low-Power Application
Sunani, S., Mahato, S. S., Panigrahy, A. K., et al. (2026) · Lecture notes in electrical engineering · doi:10.1007/978-981-92-0217-1_4
Advances and Challenges of GAA Structure Towards the 3 nm Era
Cui, J., Lyu, Y., Hu, Z., et al. (2026) · Lecture notes in electrical engineering · doi:10.1007/978-981-95-9442-9_5
Metadata
- Authors
- Bae, G., Bae, D.-I., Kang, M., Hwang, S. M., Kim, S. S., Seo, B., Kwon, T. Y., Lee, T. J., Moon, C., Choi, Y. M., Oikawa, K., Masuoka, S., Chun, K. Y., Park, S. H., Shin, H. J., Kim, J. C., Bhuwalka, K. K., Kim, D. H., Kim, W. J., Yoo, J., Jeon, H. Y., Yang, M. S., Chung, S.-J., Kim, D., Ham, B. H., Park, K. J., Kim, W. D., Park, S. H., Song, G., Kim, Y. H., Kang, M. S., Hwang, K. H., Park, C.-H., Lee, J.-H., Kim, D.-W., Jung, S.-M., & Kang, H. K.
- Affiliations
- Samsung Electronics, Samsung R&D Center, Hwasung-City, Gyeonggi-Do, Republic of Korea
- Samsung (South Korea) (KR)
- ORCID
- Venue
- 2018 IEEE International Electron Devices Meeting (IEDM)
- Publisher
- IEEE
- Published
- 2018-12
- Pages
- 28.7.1-28.7.4
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W2913404074
- Cited by
- 368
- References
- 13
- Citations by year
- 2026: 38 · 2025: 83 · 2024: 64 · 2023: 52 · 2022: 53 · 2021: 38 · 2020: 27 · 2019: 13
- FWCI
- 31.10
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Technical digest - International Electron Devices Meeting/Technical digest (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Materials Science › Materials Chemistry › 2D Materials and Applications
- Keywords
- gate-all-around MOSFET, subthreshold swing, effective channel width, standard cell design, SRAM, device reliability, low power design, effective capacitance, effective resistance
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