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3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications
Abstract
As the most feasible solution beyond FinFET technology, a gate-all-around Multi-Bridge-Channel MOSFET (MBCFET) technology is successfully demonstrated including a fully working high density SRAM. MBCFETs are fabricated using 90% or more of FinFET processes with only a few revised masks, allowing easy migration from FinFET process. Not only on-target but also multiple Vt is achieved in challengingly limited vertical spacing between channels. Also, reliability of MBCFETs is shown to be comparable to that of FinFETs. Three representative superior characteristics of MBCFET compared to FinFET have been demonstrated — better gate control with 65 mV/dec sub-threshold swing (SS) at short gate length, higher DC performance with a larger effective channel width (Weff) at reference footprint, and design flexibility with variable nanosheet (NS) widths. The optimization of the standard cell design by using variable NS width is evaluated. The usefulness of MBCFET as a multi-purpose performance provider is proven by the modulation of effective capacitance (Ceff), effective resistance (Reff) and frequency by Weff control. Finally, mass production feasibility with MBCFET is proven through a fully working high density SRAM circuit.
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“The lack of process margin to further scale fins, combined with parasitic effects that counteract performance increases at higher fin heights, means that finFETs have reached their limits of scaling and performance 96 .”
From Extreme ultraviolet lithography (2024) · cites this paper as [96]
In the citing paper
“This led to the introduction of gate -allaround field -effect transistor (GAAFET or nanosheet) technology in HVM, wherein the transistor channels are in stacked nanosheets with the gate wrapped around them 96 , 97 .”
From Extreme ultraviolet lithography (2024) · cites this paper as [96]
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Self-citationA monolithic 3D design technology co-optimization with back-end-of-line oxide channel transistor
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InfluentialSelf-citationA Novel Creation of a Multi-Bridge Channel Ferroelectric-Field Effect Transistor
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Mechanical Stress Impact on Nanosheet Device Performance
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“…(GAA) nanosheet (NS) transistors are attracting significant interest as they drive further device scaling with superior electrostatic control over Fin field effect transistors (FETs) [1] and serve as a fundamental technology for more advanced architectures such as forksheet and CFETs [2].”
Investigation of Nanosheet FETs with Embedded Gates for Enhanced DC Performance
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“In this context, global foundry businesses such as TSMC and Samsung Electronics have been developing nanosheet (NS) FETs with a gate-all-around (GAA) backbone, which is considered a promising candidate for sub-3-nm node technology [6–9].”
Rawat, A., Bhuwalka, K. K., Matagne, P., et al. (2021) · European Solid-State Circuits Conference (ESSCIRC) · doi:10.1109/esscirc53450.2021.9567879 · Cited by 1
Self-citationNovel Dual Liner Process for Side-Shielded Forksheet Device With Superior Design Margin
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MOSFETs with Stacked 2D Nanosheet Channels – An Auspicious Option to Delay “Forever”
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Noncontact Remote Doping for High-performance Two-dimensional Electronics
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Analysis and Design of MBCFET and Their Circuit Application in Current Mirror and DRAM
Kumar, T., Singh, A. P., & Mishra, V. K. (2023) · WSEAS Transactions on Circuits and Systems archive · doi:10.37394/23201.2023.22.31 · Cited by 1
Predictive Simulation of Nanosheet Transistors Including the Impact of Access Resistance
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“G ATE-ALL-AROUND field-effect transistors (GAAFETs) have emerged as the device architecture of choice for future technology nodes beyond FinFET, owing to their superior immunity to short-channel effects and increased drive current per footprint [1], [2].”
Study of 3-D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM
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Tunable HfxTi1-xO2 Dielectrics for Low-Power and High-Performance GAA Nanowire MOSFETs
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“However, broader nanosheets offer advantages over FinFETs, including higher "on" current and enhanced electrostatic performance [3,4].”
An Analytic Model for p-type Nanowire Ballistic GAA MOSFET
Cheng, H., Yang, Z., Cui, S., et al. (2025) · International Symposium on Semiconductor and Electronic Technology (ISSET) · doi:10.1109/isset66828.2025.11184919 · Cited by 1
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“As the channel length of metal–oxide–semiconductor field-effect transistors (MOSFETs) continues to shrink, FinFET devices with effective channel lengths below 5 nm have already been experimentally demonstrated [1–3].”
Chen, C.-T., Peng, K., George, T., et al. (2019) · AIP Advances · doi:10.1063/1.5088554
Spin-Based CMOS-Compatible Memories
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“With chips based on the 5nm technology node approaching production, the semiconductor industry is focusing on the 3nm technology node [1].”
MethodScaling CMOS to Nanoscale: Beyond the Planar Bulk Silicon MOSFET
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Vertical Heterojunction Ge0.92Sn0.08/Ge Gate-All-Around Nanowire pMOSFETs
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“Among those, GAA nanowire transistors have gained numerous interest due to superior gate electrostatic control and low leakage currents for ultra-scaled sub-10 nm technology nodes [1-3].”
BackgroundA unified compact model for electrostatics of III–V GAA transistors with different geometries
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Fabrication Process of MBCFET and its Characteristics
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Exploring a New Tool for Automatic Layout Synthesis for FDSOI 28 nm
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Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs
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Self-citationAdvanced process technologies for continuous logic scaling towards 2nm node and beyond (Invited)
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“Gate-all-around (GAA) improves electrostatics over FinFET and enables continuous gate length scaling.”
BackgroundInfluentialSixteen logic functions in a single electronic circuit
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Computational Study of Thermal Stress in Gate-All-Around Nanosheet Field Effect Transistor
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“In the future, Intel, Samsung, and TSMC will continue to optimize the power, performance, area, and cost (PPAC) for the logic device by using new technologies at the 2 nm technology node, such as gate-all-around FETs (GAAFETs) [2,3] and buried power rail (BPR) [4–8].”
BackgroundKing, T., & Tatum, L. P. (2023) · doi:10.1002/9781394202478.ch35
Optical Wafer Inspection at Advanced Technology Nodes
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Design and Simulation of Cylindrical Stacked Silicon Nanowire (SiNW) Field-Effect Transistors
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“GAA is projected to reduce size with increase gate-to-channel control capability, and reduce voltage [3].”
BackgroundPerformance Projection of Stacked Silicon Nanosheet-FET Architectures for Future Technology Node
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“S TAKED gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) have been widely regarded as the most promising FinFET successor to continue the CMOS scaling for sub-3-nm technology node and beyond [1], [2], [3].”
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“Gate-All-Around (GAA) nanosheet FET has been widely recognized as the mainstream logic device structure for beyond 3 nm node applications, owing to its superior gate electrostatics[1].”
Leakage Current Fluctuation of On/Off-State Stress in 3 nm Process and its Guard-band Compensation
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Assessment of Analog/RF and Linearity Parameters of n-Channel Germanium Nanosheet FETs
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Re-Examination of Uniaxial Stress Effects in Ultra-Scaled GAAFETs
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A Novel H-Shaped Fet for Enhanced Cfet Performance at Advanced Technology NodePreprint
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Towards Design-Technology Co-Optimization for Nanosheet Transistors With Backside Contact
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“Various methods have been proposed to reduce cell size, including fin depopulation technology [2] and nano-sheet FET structure [1, 9].”
The FinFET to Nanosheet Transition: A Critical Enabler for Energy-Efficient AIoT ApplicationsPreprint
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2D gate-all-around logic devices: a path toward monolithic 3D circuits beyond silicon
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Anomalous Transconductance Behavior in Mixed-Phase Negative Capacitance FETs
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“The integration of a FE layer into the gate oxide stack of nanosheet field-e ff ect transistors (NSFETs) can provide the substantial improvement in on-current ( I ON ) and o ff -current ( I OFF ), contributing to overall device performance [1], [2], [3].”
Impact of Gate-Source/Drain Underlap on Device Performance of Germanium Nanosheet FETs
Halder, A., Maity, S. K., & Dhar, R. S. (2025) · International Conference on Circuits, Power and Intelligent Systems (CCPIS) · doi:10.1109/ccpis65231.2025.11233858
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Performance Benchmark of Gate-All-Around Nanosheets Transistors Based on DTCO Simulation
Wu, C., Ma, J., Gu, H., et al. (2025) · IEEE International Conference on ASIC (ASICON) · doi:10.1109/asicon66040.2025.11325857
“…nanosheet Gate-All-Around (GAA) field-effect transistor (GAAFET) has been recognized as the alternative logic device for 3 nm node and beyond applications, owing to its superior electrostatics and enlarged effective channel width (W eff ) per active footprint compared with that of FinFET [1-2].”
Performance Comparison Between Bulk-Si and FDSOI Nanosheet GAAFETs
RS.He, BX.Gan, S.Cristoloveanu, et al. (2025) · IEEE International Conference on ASIC (ASICON) · doi:10.1109/asicon66040.2025.11326232
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“Because of the high process complexity of FinFETs and gate-all-around (GAA) structure, wafer-scale monolithic heterogeneous integration is gradually emerging as a candidate for miniaturized CMOS circuits in the next generation [2], [3].”
Parasitic Capacitance Analysis in Tapered CFET Devices for Advanced Technology Nodes
Pal, J., & Mohapatra, N. R. (2025) · IEEE International Conference on Emerging Electronics (ICEE) · doi:10.1109/icee67165.2025.11409786
NPUWattch: ML-Based Power, Area, and Timing Modeling for Neural Accelerators
Kim, S., Kim, M., Park, C., et al. (2026) · Proceedings - International Symposium on High-Performance Computer Architecture/Proceedings · doi:10.1109/hpca68181.2026.11408488
“The device characteristics of the latest transistors have already been well established through experiments on real silicon [3], [21], [45].”
Self-citationDewangan, R. K., Singh, V. K., & Khan, M. R. (2026) · Progress in Nanoscience and Nanotechnology · doi:10.2174/0122106812429155251203054946
Park, H. R., & Kim, T. (2026) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1109/asp-dac66049.2026.11420461
“…superior electrostatic control compared to planar MOSFETs but encounter fundamental scaling challenges at technology nodes below 3nm. NSFETs ([2], [3]) achieve improved PPA by enclosing the channel and enabling vertical stacking of nanosheets, effectively eliminating the need for lateral spacing…”
Lee, S., Hong, S., Park, M., Kim, S., Baek, S., Yang, S., Lee, C. Y., Bae, S., Suh, J., Lee, Y., et al. (2026) · Advanced Functional Materials · doi:10.1002/adfm.202532204 · Cited by 1
Self-citationPreferential Halogen Adsorption on Si, Ge, and SiGe Surfaces for Selective Etching
Longo, R. C., Conlin, P., Sridhar, S., et al. (2026) · ACS Applied Engineering Materials · doi:10.1021/acsaenm.6c00186
An Artificial Neural NetworkAssisted Charge-Based Compact Model for Advanced Multi-Gate FETs
Singh, A., Behera, A. K., & Dasgupta, A. (2026) · IEEE Electron Devices Technology & Manufacturing Conference (EDTM) · doi:10.1109/edtm65772.2026.11497512
“To maintain high accuracy, existing industry-standard compact models incorporate extensive physical details, which increase computational complexity and significantly reduce simulation speed [2], [3].”
Metadata
- Authors
- Bae, G., Bae, D.-I., Kang, M., Hwang, S. M., Kim, S. S., Seo, B., Kwon, T. Y., Lee, T. J., Moon, C., Choi, Y. M., Oikawa, K., Masuoka, S., Chun, K. Y., Park, S. H., Shin, H. J., Kim, J. C., Bhuwalka, K. K., Kim, D. H., Kim, W. J., Yoo, J., Jeon, H. Y., Yang, M. S., Chung, S.-J., Kim, D., Ham, B. H., Park, K. J., Kim, W. D., Park, S. H., Song, G., Kim, Y. H., Kang, M. S., Hwang, K. H., Park, C.-H., Lee, J.-H., Kim, D.-W., Jung, S.-M., & Kang, H. K.
- Affiliations
- Samsung Electronics, Samsung R&D Center, Hwasung-City, Gyeonggi-Do, Republic of Korea
- Samsung (South Korea) (KR)
- ORCID
- Venue
- 2018 IEEE International Electron Devices Meeting (IEDM)
- Publisher
- IEEE
- Published
- 2018-12
- Pages
- 28.7.1-28.7.4
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W2913404074
- Cited by
- 368
- References
- 13
- Citations by year
- 2026: 38 · 2025: 83 · 2024: 64 · 2023: 52 · 2022: 53 · 2021: 38 · 2020: 27 · 2019: 13
- FWCI
- 31.10
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Technical digest - International Electron Devices Meeting/Technical digest (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Materials Science › Materials Chemistry › 2D Materials and Applications
- Keywords
- gate-all-around MOSFET, subthreshold swing, effective channel width, standard cell design, SRAM, device reliability, low power design, effective capacitance, effective resistance
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Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
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