Cited by 1,695Analog and Mixed-Signal Circuit DesignRadio Frequency Integrated Circuit DesignLow-power high-performance VLSI design

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A low-power low-noise cmos for amplifier neural recording applications

Harrison, R.R., Charles, C.·2003·IEEE Journal of Solid-State Circuits

DOI 10.1109/jssc.2003.811979

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Abstract

There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-μm CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 μVrms and a power dissipation of 80 μW while consuming 0.16 mm2of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 μW while maintaining a similar noise-power tradeoff.

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Authors: Harrison, R. R., & Charles, C.
Affiliations: University of Utah (US)
Venue: IEEE Journal of Solid-State Circuits
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Published: 2003-06
Volume: 38
Issue: 6
Pages: 958-965
ISSN: 0018-9200 (ISSN-L)
DOI: 10.1109/jssc.2003.811979
OpenAlex: W2159318368
Cited by: 1,695
References: 33
Citations by year: 2026: 41 · 2025: 55 · 2024: 71 · 2023: 71 · 2022: 74 · 2021: 118 · 2020: 82 · 2019: 80 · 2018: 93 · 2017: 86 · 2016: 90 · 2015: 90 · 2014: 85 · 2013: 80 · 2012: 82
FWCI: 24.78
Type: journal article
Language: en
Open access: closed
Licence: ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html (vor)
Locations: IEEE Journal of Solid-State Circuits (publishedVersion)
Topics: Physical Sciences › Engineering › Electrical and Electronic Engineering › Analog and Mixed-Signal Circuit Design
Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
Keywords: neural recording, DC offset rejection, noise efficiency factor, weak and strong inversion, VLSI design

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A low-power low-noise cmos for amplifier neural recording applications

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