A 1-V 0.25- $\mu \text{W}$ Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor
Abstract
This paper presents a highly power-efficient amplifier. By stacking inverters and splitting the capacitor feedback network, the proposed amplifier achieves six-time current reuse, thereby significantly boosting the transconductance and lowering noise but without increasing the current consumption. A novel biasing scheme is devised to ensure robust operation under 1-V supply. A prototype in 180-nm CMOS has 5.5-μVrmsnoise within 10-kHz BW while consuming only 0.25-μW power, leading to a noise efficiency factor of 1.07, which is the best among reported amplifiers.
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Typical NEF values range from just above 1 to around 12 in neural recording front-ends.
“Typical NEF values range from just above 1 to around 12 in neural recording front-ends [166].”
From Active Neural Interface Circuits and Systems for Selective Control of Peripheral Nerves: A Review (2024) · cites this paper as [166]
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- Authors
- Shen, L., Lu, N., & Sun, N.
- Affiliations
- The University of Texas at Austin (US)
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 2018-03
- Volume
- 53
- Issue
- 3
- Pages
- 896-905
- ISSN
- 0018-9200 (ISSN-L)
- 1558-173X
- OpenAlex
- W2783410960
- Cited by
- 101
- References
- 29
- Citations by year
- 2026: 8 · 2025: 21 · 2024: 14 · 2023: 11 · 2022: 10 · 2021: 15 · 2020: 8 · 2019: 11 · 2018: 3
- FWCI
- 3.70
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Journal of Solid-State Circuits (publishedVersion)
- Funders
- NSF (1254459, 1509767, 1527320)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Keywords
- low-voltage amplifier, low-power amplifier, noise efficiency factor, current reuse, biasing scheme, transconductance, 0.18 μm CMOS
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