A 0.013 ${\hbox {mm}}^{2}$, 5 $\mu\hbox{W}$, DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply
Abstract
We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology and an compact, boxcar sampling ADC are used to cancel input offset and prevent noise folding while enabling “per-pixel” digitization, alleviating system-level complexity. Implemented in a 65 nm CMOS process, the prototype occupies 0.013 mm2while consuming 5 μW and achieving 4.9 μVrms of input-referred noise in a 10 kHz bandwidth.
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Modern circuit designs and IC fabrication technologies have produced innovative designs that allow designers to relax the size-functionality compromises.
“However, modern circuit designs [77, 92] and IC fabrication technologies [18, 86] have resulted in innovative designs, enabling designers to relax such compromises.”
From Implantable neurotechnologies: a review of integrated circuit neural amplifiers (2016) · cites this paper as [86]
Neural amplifier ICs have been created that capture both action potentials and local field potentials, with separate filtering, amplification and output for each signal type.
“CNS amplifiers have also been developed that can acquire both types of signals, separately filtering, amplifying and outputting each signal type [46, 86, 100].”
From Implantable neurotechnologies: a review of integrated circuit neural amplifiers (2016) · cites this paper as [86]
Muller et al. introduced the power efficiency factor, which accounts for both operating current and supply voltage and therefore provides a better comparison of amplifier performance.
“Recently, Muller et al. [86] introduced the power efficiency factor (PEF), which takes into account both the operating current and the supply voltage and therefore provides a better comparison of the amplifier’s performance.”
From Implantable neurotechnologies: a review of integrated circuit neural amplifiers (2016) · cites this paper as [86]
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Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes
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A Sub-${\mu}$W/Ch Analog Front-End for $\Delta $-Neural Recording With Spike-Driven Data Compression
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A 10 kPixel CMOS Hall Sensor Array With Baseline Suppression and Parallel Readout for Immunoassays
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An Inductively-Powered Wireless Neural Recording System With a Charge Sampling Analog Front-End
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A Dual-Loop Eight-Channel ECG Recording System With Fast Settling Mode for 12-Lead Applications
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Nikas, A., Jambunathan, S., Klein, L., Voelker, M., & Ortmanns, M. (2019) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2019.2931811 · Cited by 45 · see citing works
Wendler, D., Dorigo, D. D., Amayreh, M., Bleitner, A., Marx, M., Willaredt, R., & Manoli, Y. (2022) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2022.3190446 · Cited by 44 · see citing works
Song, L., & Rahmat‐Samii, Y. (2017) · IEEE Transactions on Antennas and Propagation · doi:10.1109/tap.2017.2700163 · Cited by 44 · see citing works
A 0.01-mm 2 Mostly Digital Capacitor-Less AFE for Distributed Autonomous Neural Sensor Nodes
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A Digitally Assisted, Signal Folding Neural Recording Amplifier
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A Frequency Shaping Neural Recorder With 3 pF Input Capacitance and 11 Plus 4.5 Bits Dynamic Range
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A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip
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A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression
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Self-citationA Low-Power Configurable Neural Recording System for Epileptic Seizure Detection
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A 0.6V 3.8μW ECG/bio-impedance monitoring IC for disposable health patch in 40nm CMOS
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An AC-Coupled 1st-Order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition
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Current-Efficient Preamplifier Architecture for CMRR Sensitive Neural Recording Applications
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A Compact Sub-μW CMOS ECG Amplifier With 57.5-MΩ Zin, 2.02 NEF, 8.16 PEF and 83.24-dB CMRR
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Brain–computer interfaces in 2023–2024
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24.1 A miniaturized 64-channel 225μW wireless electrocorticographic neural sensor
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Self-citationCMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing
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Design considerations for effective neural signal sensing and amplification: a review
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Actively Multiplexed μECoG Brain Implant System With Incremental-ΔΣ ADCs Employing Bulk-DACs
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A 0.5-V power-efficient low-noise CMOS instrumentation amplifier for wireless biosensor
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Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS
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CMOS Interfaces for Internet-of-Wearables Electrochemical Sensors: Trends and Challenges
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Yoon, Y., Choi, D., & Roh, J. (2015) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2015.2468857 · Cited by 27 · see citing works
- Authors
- Muller, R., Gambini, S., & Rabaey, J. M.
- Affiliations
- University of California, Berkeley (US)
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 2012-01
- Volume
- 47
- Issue
- 1
- Pages
- 232-243
- ISSN
- 0018-9200 (ISSN-L)
- 1558-173X
- OpenAlex
- W2003444784
- Cited by
- 338
- References
- 27
- Citations by year
- 2026: 11 · 2025: 23 · 2024: 18 · 2023: 21 · 2022: 22 · 2021: 26 · 2020: 26 · 2019: 25 · 2018: 34 · 2017: 28 · 2016: 25 · 2015: 26 · 2014: 26 · 2013: 20 · 2012: 7
- FWCI
- 10.04
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Journal of Solid-State Circuits (publishedVersion)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Life Sciences › Neuroscience › Cellular and Molecular Neuroscience › Neuroscience and Neural Engineering
- Keywords
- neural signal acquisition, low-power integrated circuits, local field potentials, digital-to-analog converter, noise folding, low-voltage operation, 65 nm CMOS, area-efficient circuit design
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