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Cited by 3Induction Heating and Inverter TechnologyElectric Power Systems and ControlMultilevel Inverters and Converters

The DOI matches its Crossref record; 45 of the 46 references it cites were found in a registry or an index; none of the 42 sources its claims cite is checked for support yet.

Design, Analysis and Experimental Verification of the Self-Resonant Inverter for Induction Heating Crucible Melting Furnace Based on IGBTs Connected in Parallel

Open access
Dimitrov, Borislav, Hayatleh, Khaled, Barker, Steve, Collier, Gordana·2021·Electricity
DOI 10.3390/electricity2040026
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Abstract

The object of this research was a self-resonated inverter, based on paralleled Insulated-Gate Bipolar Transistors (IGBTs), for high-frequency induction heating equipment, operating in a wide range of output powers, applicable for research and industrial purposes. For the nominal installed capacity for these types of invertors to be improved, the presented inverter with a modified circuit comprising IGBT transistors connected in parallel was explored. The suggested topology required several engineering problems to be solved: minimisation of the current mismatch amongst the paralleled transistors; a precise analysis of the dynamic and static transistors’ parameters; determination of the derating and mismatch factors necessary for a reliable design; experimental verification confirming the applicability of the suggested topology in the investigated inverter. This paper presents the design and analysis of IGBT transistors based on datasheet parameters and mathematical apparatus application. The expected current mismatch and the necessary derating factor, based on the expected mismatch in transistor parameters in a production lot, were determined. The suggested design was experimentally tested and investigated using a self-resonant inverter model in a melting crucible induction laboratory furnace.

Overview

CoChat Summary

TL;DR

The paper designs and experimentally verifies a self-resonant induction-heating inverter using paralleled IGBTs, with a datasheet-digitalization methodology to estimate current mismatch and derating. It reports stable ZVS operation, acceptable current sharing (2–5% same-lot, <2% after layout improvement), and feasibility of >30 kW with four IGBTs per side.

Key findings

  • For a target maximum current of \(I_{\max}=160\) A and accepted derating \(\Delta=0.2\) (20%), the design uses four IGBTs in parallel per side, with datasheet transistor current \(I_C=50\) A and expected current per transistor of 40 A.
  • At \(V_{ge}=9\) V, expected maximum collector currents vary with temperature and parameter spread: \(I_{C\max(150^\circ C,\min)}=40.91\) A, \(I_{C\max(150^\circ C,\max)}=44.75\) A, \(I_{C\max(25^\circ C,\min)}=52.41\) A, and \(I_{C\max(25^\circ C,\max)}=56.99\) A; worst-case current can vary by 16 A, while same-thermal-condition maximum-temperature mismatch is 4.58 A (under 20%).
  • Derating analysis for \(V_{ge}=9\)–10 V gives worst-case \(\Delta=0.12\)–0.21, but with shared thermal equilibrium the required derating is only \(\Delta=0.034\)–0.053 (3.4%–5.3%).
  • Experiments showed same-production-lot current mismatch of 2–5% at the peak, different-lot transistors with 25% higher current and 540 ns switch-on delay, improved layout mismatch under 2%, thermal difference up to 10 °C between Q1 and Q4, and 3–4 °C between same-lot Q1 and Q2; the crucible reached 500 °C for 10 min, enough for melting tin.

Methods

  • Design/analysis: a self-resonant inverter topology with paralleled RC-IGBTs; the methodology estimates derating factor and total current, selects IGBTs, digitalizes datasheet transconductance and output characteristics into 4–6 degree polynomial equations, assumes ±5% production-lot parameter variation, and calculates mismatch factor \(M\) and derating \(\Delta\).
  • Experimental setup: converters were built with 3, 4, and 5 transistors in parallel per side using IGBTs from the same and different production lots; currents through each transistor were measured at full load during the entire melting cycle, with thermal differences measured by infrared camera on the heatsink surface.
  • Measurement conditions: resonant frequency varied from 25–35 kHz depending on load; equipment included oscilloscope RS PRO RSDS1204CFL, current probe ELDITEST CP6220, and voltage differential probe Pico; tests used a graphene crucible and forced air cooling.

Limitations

  • Paper-stated: the suggested methodology was based on stipulated data, and Equations (3)–(6) were derived only for the concrete transistor, so it did not have diverse characteristics.
  • Paper-stated: the converter layout was not an object of this research; parasitics-minimisation effects were experimentally observed but require future research and improvements.
  • Evident from the text: experimental validation is limited to specific IGBT types and a laboratory setup, and thermal tests intentionally separated paralleled transistors rather than using a typical shared heatsink, so thermal equalisation results may not represent standard assembly.

Model-written summary. Check it against the paper before relying on it.

Integrity signals

Registry

Crossref · 10.3390/electricity2040026

Cites

45 of 45 references verified0 citation errors · 0 not checkable

Statistics

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Figures

Figure 1 The electronic circuit of the proposed inverter for induction heating crucible melting furnace. Q1-Q8 IGBT transistors; GD1-GD8 gate drivers; C1, L1, L2 resonance tank; L3 induction heating inductor. A block diagram of the entire system for induction heating. Figure 1. The electronic circuit of the proposed inverter for induction heating crucible melting furnace. Q1-Q8 IGBT transistors; GD1-GD8 gate drivers; C1, L1, L2 resonance tank; L3 induction heating inductor. A block diagram of the entire system for induction heating.
Figure 1 The electronic circuit of the proposed inverter for induction heating crucible melting furnace. Q1-Q8 IGBT transistors; GD1-GD8 gate drivers; C1, L1, L2 resonance tank; L3 induction heating inductor. A block diagram of the entire system for induction heating. Figure 1. The electronic circuit of the proposed inverter for induction heating crucible melting furnace. Q1-Q8 IGBT transistors; GD1-GD8 gate drivers; C1, L1, L2 resonance tank; L3 induction heating inductor. A block diagram of the entire system for induction heating.CC-BY · From the PDF
Figure 2 Analysis of the number of IGBTs in parallel. ( A ) Number of transistors in parallel calculated in a derating range ∆ = 0.1 - 0.5 , giving the necessary nominal current per transistor; ( B ) expected current through each transistor at the assumed maximum current of 𝐼௠௔௫ = 160𝐴 ; ( C ) the targeted derating of ∆ = 0.2 , i.e. 20%, is feasible with 𝐼஼ா௡௢௠ = 50𝐴, 4 IGBTs in parallel. Figure 2. Analysis of the number of IGBTs in parallel. ( A ) Number of transistors in parallel calculated in a derating range D = 0.1 -0.5, giving the necessary nominal current per transistor; ( B ) expected current through each transistor at the assumed maximum current of Imax = 160 A; ( C ) the targeted derating of D = 0.2, i.e., 20%, is feasible with ICEnom = 50 A, 4 IGBTs in parallel. Figure 2. Analysis of the number of IGBTs in parallel. ( A ) Number of transistors in parallel calculated in a derating range ∆ = 0.1 - 0.5 , giving the necessary nominal current per transistor; ( B ) expected current through each transistor at the assumed maximum current of 𝐼௠௔௫ = 160𝐴 ; ( C ) the
Figure 2 Analysis of the number of IGBTs in parallel. ( A ) Number of transistors in parallel calculated in a derating range ∆ = 0.1 - 0.5 , giving the necessary nominal current per transistor; ( B ) expected current through each transistor at the assumed maximum current of 𝐼௠௔௫ = 160𝐴 ; ( C ) the targeted derating of ∆ = 0.2 , i.e. 20%, is feasible with 𝐼஼ா௡௢௠ = 50𝐴, 4 IGBTs in parallel. Figure 2. Analysis of the number of IGBTs in parallel. ( A ) Number of transistors in parallel calculated in a derating range D = 0.1 -0.5, giving the necessary nominal current per transistor; ( B ) expected current through each transistor at the assumed maximum current of Imax = 160 A; ( C ) the targeted derating of D = 0.2, i.e., 20%, is feasible with ICEnom = 50 A, 4 IGBTs in parallel. Figure 2. Analysis of the number of IGBTs in parallel. ( A ) Number of transistors in parallel calculated in a derating range ∆ = 0.1 - 0.5 , giving the necessary nominal current per transistor; ( B ) expected current through each transistor at the assumed maximum current of 𝐼௠௔௫ = 160𝐴 ; ( C ) theCC-BY · From the PDF
Figure 3 ( A ) IGBT transconductance characteristic and its dependence on the temperature; NTCNegative Thermal Coefficient; PTC-Positive Thermal Coefficient; ITP-Isothermal Point; ( B ) IGBT output characteristics and its dependence on the temperature. Figure 3. ( A ) IGBT transconductance characteristic and its dependence on the temperature; NTCNegative Thermal Coefficient; PTC-Positive Thermal Coefficient; ITP-Isothermal Point; ( B ) IGBT output characteristics and its dependence on the temperature. Figure 3. ( A ) IGBT transconductance characteristic and its dependence on the temperature; NTCNegative Thermal Coefficient; PTC-Positive Thermal Coefficient; ITP-Isothermal Point; ( B ) IGBT output characteristics and its dependence on the temperature.
Figure 3 ( A ) IGBT transconductance characteristic and its dependence on the temperature; NTCNegative Thermal Coefficient; PTC-Positive Thermal Coefficient; ITP-Isothermal Point; ( B ) IGBT output characteristics and its dependence on the temperature. Figure 3. ( A ) IGBT transconductance characteristic and its dependence on the temperature; NTCNegative Thermal Coefficient; PTC-Positive Thermal Coefficient; ITP-Isothermal Point; ( B ) IGBT output characteristics and its dependence on the temperature. Figure 3. ( A ) IGBT transconductance characteristic and its dependence on the temperature; NTCNegative Thermal Coefficient; PTC-Positive Thermal Coefficient; ITP-Isothermal Point; ( B ) IGBT output characteristics and its dependence on the temperature.CC-BY · From the PDF
Figure 4 ( A ) Transconductance (dynamic) characteristics at nominal 25 °C (graphic 1 maximum and 2 minimum) and maximum 150 °C (graphic 3 maximum and 4 minimum) temperatures. ( B ) Output (static) characteristics at nominal 25 °C (graphic 1 maximum and 2 minimum) and maximum 150 °C (graphic 3 maximum and 4 minimum) temperatures. Figure 4. ( A ) Transconductance (dynamic) characteristics at nominal 25 ◦ C (graphic 1 maximum and 2 minimum) and maximum 150 ◦ C (graphic 3 maximum and 4 minimum) temperatures. ( B ) Output (static) characteristics at nominal 25 ◦ C (graphic 1 maximum and 2 minimum) and maximum 150 ◦ C (graphic 3 maximum and 4 minimum) temperatures.
Figure 4 ( A ) Transconductance (dynamic) characteristics at nominal 25 °C (graphic 1 maximum and 2 minimum) and maximum 150 °C (graphic 3 maximum and 4 minimum) temperatures. ( B ) Output (static) characteristics at nominal 25 °C (graphic 1 maximum and 2 minimum) and maximum 150 °C (graphic 3 maximum and 4 minimum) temperatures. Figure 4. ( A ) Transconductance (dynamic) characteristics at nominal 25 ◦ C (graphic 1 maximum and 2 minimum) and maximum 150 ◦ C (graphic 3 maximum and 4 minimum) temperatures. ( B ) Output (static) characteristics at nominal 25 ◦ C (graphic 1 maximum and 2 minimum) and maximum 150 ◦ C (graphic 3 maximum and 4 minimum) temperatures.CC-BY · From the PDF
Figure 5 ( A ) Expected variation in the derating factor; ( B ) expected variation in the maximum current through the paralleled transistors. Graphics 1 and 2 at maximum and minimum thermal difference. Figure 5. ( A ) Expected variation in the derating factor; ( B ) expected variation in the maximum current through the paralleled transistors. Graphics 1 and 2 at maximum and minimum thermal difference.
Figure 5 ( A ) Expected variation in the derating factor; ( B ) expected variation in the maximum current through the paralleled transistors. Graphics 1 and 2 at maximum and minimum thermal difference. Figure 5. ( A ) Expected variation in the derating factor; ( B ) expected variation in the maximum current through the paralleled transistors. Graphics 1 and 2 at maximum and minimum thermal difference.CC-BY · From the PDF
Figure 6 A model of self-resonant converter for induction heating: 1-IGBT transistors; 2-resona capacitor tank; 3-inductor; 4-graphene crucible. The used measurement equipment is as follow oscilloscope RS PRO RSDS1204CFL; current probe ELDITEST CP6220; voltage differential pro Figure 6. Amodel of self-resonant converter for induction heating: 1-IGBT transistors; 2-resonant capacitor tank; 3-inductor; 4-graphene crucible. The used measurement equipment is as follows: oscilloscope RS PRO RSDS1204CFL; current probe ELDITEST CP6220; voltage differential probe Pico.
Figure 6 A model of self-resonant converter for induction heating: 1-IGBT transistors; 2-resona capacitor tank; 3-inductor; 4-graphene crucible. The used measurement equipment is as follow oscilloscope RS PRO RSDS1204CFL; current probe ELDITEST CP6220; voltage differential pro Figure 6. Amodel of self-resonant converter for induction heating: 1-IGBT transistors; 2-resonant capacitor tank; 3-inductor; 4-graphene crucible. The used measurement equipment is as follows: oscilloscope RS PRO RSDS1204CFL; current probe ELDITEST CP6220; voltage differential probe Pico.CC-BY · From the PDF
Figure 7 Current mismatch amongst four paralleled IGBT transistors. ( A , B ) switched-on with delay of transistor 4; ( C ) switched-on prematurely of transistor 4; 1, 2-transistors with the sam production lot; 3, 4-two different production lots. Figure 7. Current mismatch amongst four paralleled IGBT transistors. ( A , B ) switched-on with a delay of transistor 4; ( C ) switched-on prematurely of transistor 4; 1, 2-transistors with the same production lot; 3, 4-two different production lots.
Figure 7 Current mismatch amongst four paralleled IGBT transistors. ( A , B ) switched-on with delay of transistor 4; ( C ) switched-on prematurely of transistor 4; 1, 2-transistors with the sam production lot; 3, 4-two different production lots. Figure 7. Current mismatch amongst four paralleled IGBT transistors. ( A , B ) switched-on with a delay of transistor 4; ( C ) switched-on prematurely of transistor 4; 1, 2-transistors with the same production lot; 3, 4-two different production lots.CC-BY · From the PDF
Figure 8 Minimum current mismatch amongst four IGBT transistors from the same prod Figure 8. Minimum current mismatch amongst four IGBT transistors from the same production lot.
Figure 8 Minimum current mismatch amongst four IGBT transistors from the same prod Figure 8. Minimum current mismatch amongst four IGBT transistors from the same production lot.CC-BY · From the PDF
Figure 9 Operation of the inverter for induction heating. ( A , B ) 1, 2-voltages, respectively, o paralleled high side (Q1, Q3, Q5, Q7-Figure 1) and low side (Q2, Q4, Q6, Q8-Figure 1) trans 3-current through the inductor; ( B ): 4-voltage crossing the zero switching point. Figure 9. Operation of the inverter for induction heating. ( A , B ) 1, 2-voltages, respectively, over the paralleled high side (Q1, Q3, Q5, Q7-Figure 1) and low side (Q2, Q4, Q6, Q8-Figure 1) transistors; 3-current through the inductor; ( B ): 4-voltage crossing the zero switching point.
Figure 9 Operation of the inverter for induction heating. ( A , B ) 1, 2-voltages, respectively, o paralleled high side (Q1, Q3, Q5, Q7-Figure 1) and low side (Q2, Q4, Q6, Q8-Figure 1) trans 3-current through the inductor; ( B ): 4-voltage crossing the zero switching point. Figure 9. Operation of the inverter for induction heating. ( A , B ) 1, 2-voltages, respectively, over the paralleled high side (Q1, Q3, Q5, Q7-Figure 1) and low side (Q2, Q4, Q6, Q8-Figure 1) transistors; 3-current through the inductor; ( B ): 4-voltage crossing the zero switching point.CC-BY · From the PDF
Image 10
CC-BY · From the PDF
Figure 11 Infrared temperature measurements on the surface of the heatsink. ( A , C ) Appropriately selected transistors from the same production lot (Figure 7, graphics 1, 2); ( B , D ) transistors from different production lots (Figure 7 graphics 1, 4). The thermal measurements were performed with the infrared camera FLIR. Figure 11. Infrared temperature measurements on the surface of the heatsink. ( A , C ) Appropriately selected transistors from the same production lot (Figure 7, graphics 1, 2); ( B , D ) transistors from different production lots (Figure 7 graphics 1, 4). The thermal measurements were performed with the infrared camera FLIR.
Figure 11 Infrared temperature measurements on the surface of the heatsink. ( A , C ) Appropriately selected transistors from the same production lot (Figure 7, graphics 1, 2); ( B , D ) transistors from different production lots (Figure 7 graphics 1, 4). The thermal measurements were performed with the infrared camera FLIR. Figure 11. Infrared temperature measurements on the surface of the heatsink. ( A , C ) Appropriately selected transistors from the same production lot (Figure 7, graphics 1, 2); ( B , D ) transistors from different production lots (Figure 7 graphics 1, 4). The thermal measurements were performed with the infrared camera FLIR.CC-BY · From the PDF
Figure 12 Transistors thermal difference for one melting cycle of 10 min. ( A ) Between tran Q1 and Q4; ( B ) between transistors Q1 and Q2, both selected according to Figure 7A. Figure 12. Transistors thermal difference for one melting cycle of 10 min. ( A ) Between transistors Q1 and Q4; ( B ) between transistors Q1 and Q2, both selected according to Figure 7A. Figure 12. Transistors thermal difference for one melting cycle of 10 min. ( A ) Between transisto Q1 and Q4; ( B ) between transistors Q1 and Q2, both selected according to Figure 7A.
Figure 12 Transistors thermal difference for one melting cycle of 10 min. ( A ) Between tran Q1 and Q4; ( B ) between transistors Q1 and Q2, both selected according to Figure 7A. Figure 12. Transistors thermal difference for one melting cycle of 10 min. ( A ) Between transistors Q1 and Q4; ( B ) between transistors Q1 and Q2, both selected according to Figure 7A. Figure 12. Transistors thermal difference for one melting cycle of 10 min. ( A ) Between transisto Q1 and Q4; ( B ) between transistors Q1 and Q2, both selected according to Figure 7A.CC-BY · From the PDF
Figure 13 Infrared image of the graphene crucible, given in Figure 6. Figure 13. Infrared image of the graphene crucible, given in Figure 6.
Figure 13 Infrared image of the graphene crucible, given in Figure 6. Figure 13. Infrared image of the graphene crucible, given in Figure 6.CC-BY · From the PDF
Figure 14 Oscillations due to PCB layout issues. Figure 14. Oscillations due to PCB layout issues. Figure 14. Oscillations due to PCB layout issues.
Figure 14 Oscillations due to PCB layout issues. Figure 14. Oscillations due to PCB layout issues. Figure 14. Oscillations due to PCB layout issues.CC-BY · From the PDF
Figure 15 A suggested structure of connection. Figure 15. Asuggested structure of connection.
Figure 15 A suggested structure of connection. Figure 15. Asuggested structure of connection.CC-BY · From the PDF

Verification

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Citations

Cites

Research works printed but not linked: 1

  1. Dimitrov, 2014, An Approach for Designing a Complex Inductor—Workpiece System for Induction Heating Detail Systems, Technol. Educ. Manag. Inform. TEM J., 3, 244

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Metadata

Authors
Dimitrov, B., Hayatleh, K., Barker, S., & Collier, G.
Affiliations
  • University of Warwick (GB)
  • Oxford Brookes University (GB)
Corresponding author
Dimitrov, Borislav
ORCID
Venue
Electricity
Publisher
MDPI AG
Published
2021-10-11
Volume
2
Issue
4
Pages
439-458
ISSN
2673-4826 (ISSN-L)
DOI
10.3390/electricity2040026
OpenAlex
W3206514520
Semantic Scholar
08b78cdc34f3fcae1dd607ad2c0a31e04bc2b654
Cited by
3
References
46
Citations by year
2025: 2 · 2024: 1
FWCI
0.07
Type
journal article
Language
en
Open access
Licence
Locations
  • Electricity (publishedVersion, cc-by)
  • Warwick Research Archive Portal (University of Warwick) (acceptedVersion)
  • DOAJ (DOAJ: Directory of Open Access Journals) (submittedVersion, cc-by-sa)
  • Radar (Oxford Brookes University) (submittedVersion, cc-by)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Induction Heating and Inverter Technology
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Electric Power Systems and Control
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Multilevel Inverters and Converters
Keywords
induction heating, current mismatch, derating factor, transistor parameter variation, high-frequency power conversion, inverter topology design

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