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3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications
Abstract
As the most feasible solution beyond FinFET technology, a gate-all-around Multi-Bridge-Channel MOSFET (MBCFET) technology is successfully demonstrated including a fully working high density SRAM. MBCFETs are fabricated using 90% or more of FinFET processes with only a few revised masks, allowing easy migration from FinFET process. Not only on-target but also multiple Vt is achieved in challengingly limited vertical spacing between channels. Also, reliability of MBCFETs is shown to be comparable to that of FinFETs. Three representative superior characteristics of MBCFET compared to FinFET have been demonstrated — better gate control with 65 mV/dec sub-threshold swing (SS) at short gate length, higher DC performance with a larger effective channel width (Weff) at reference footprint, and design flexibility with variable nanosheet (NS) widths. The optimization of the standard cell design by using variable NS width is evaluated. The usefulness of MBCFET as a multi-purpose performance provider is proven by the modulation of effective capacitance (Ceff), effective resistance (Reff) and frequency by Weff control. Finally, mass production feasibility with MBCFET is proven through a fully working high density SRAM circuit.
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FinFETs have reached their limits of scaling and performance due to lack of process margin and parasitic effects.
“The lack of process margin to further scale fins, combined with parasitic effects that counteract performance increases at higher fin heights, means that finFETs have reached their limits of scaling and performance 96 .”
From Extreme ultraviolet lithography (2024) · cites this paper as [96]
GAAFET (nanosheet) technology was introduced in HVM, wherein transistor channels are in stacked nanosheets with the gate wrapped around them.
“This led to the introduction of gate -allaround field -effect transistor (GAAFET or nanosheet) technology in HVM, wherein the transistor channels are in stacked nanosheets with the gate wrapped around them 96 , 97 .”
From Extreme ultraviolet lithography (2024) · cites this paper as [96]
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“In order to achieve a compatible fabrication approach with the mainstream FinFET process and improve the driving ability of the GAA NW/NS devices, stacked GAA Si NW/NS FETs have been proposed using conventional gate-last process, which provides a simple integration method by releasing NW channels from multilayer epita…”
MethodBSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs
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“Silicon technology has reached the nano-CMOS era with 10 and 7 nm Fin Field-Effect Transistors (FinFETs) CMOS technologies [3–7] in mass production and 5 nm and 3 nm Gate-All-Around (GAA) NanoWire Field Effect Transistors (NWFETs) in development stage [8].”
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“date for the ultrascaled sub-10-nm technology nodes, which necessitate superior gate electrostatic control and suppressed short-channel effects [2]–[4].”
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Self-citationPerformance limit of all-wrapped monolayer MoS2 transistors
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Self-citationGT3: An Open-Source 3-nm GAAFET PDK and Platform for End-to-End Evaluation of Emerging Technologies
Shim, D. E., Kumar, P., Kini, A. A., et al. (2025) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2025.3540760 · Cited by 12
“Many research groups focus on novel device architectures [3], [4], interconnect options [5], and packaging solutions [6], which are all critical components moving forward.”
Yang, J., Chen, K., Wang, D., et al. (2023) · Micromachines · doi:10.3390/mi14030611 · Cited by 11
“Compared with the traditional bulk FinFET architecture, stacked Si nanosheet devices are fabricated thanks to the epitaxial growth of Si/SiGe multilayers, Si/SiGe highly selective etching and the conformal deposition of high-k dielectrics/metal gate (HKMG) stacks in between the Si nanosheets [11].”
BackgroundLee, G., & Choi, Y. (2020) · IEEE Electron Device Letters · doi:10.1109/led.2020.3022025 · Cited by 11
“INTRODUCTION THE gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor has attracted considerable attention because it provides superior gate controllability to suppress short-channel effects [1].”
BackgroundSelf-citationYadav, N., Jadav, S., & Saini, G. (2022) · Silicon · doi:10.1007/s12633-022-01989-w · Cited by 11
“Stacked nanosheet FET or Multi-Bridge channel FET (MBCFET) at 3 nm provides 30 % improvement in performance along with 50 % and 45 % reduction in power consumption and area respectively in comparison to 7 nm technology [21].”
BackgroundNS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance
Mo, F., Spano, C. E., Ardesi, Y., et al. (2023) · Electronics · doi:10.3390/electronics12061487 · Cited by 11
“Furthermore, our results match the literature’s theoretical and experimental results for the different target applications [5,10,12,14].”
BackgroundMethodResultInfluentialGate-All-Around FET Design Rule for Suppression of Excess Non-Linearity
Dasgupta, A., & Hu, C. C. (2020) · IEEE Electron Device Letters · doi:10.1109/led.2020.3032390 · Cited by 11
Novel Complementary Field-Effect Transistors With Tree-Type Channel for 3-nm Technology Node
Zhao, J., Zou, X., Shen, Y., et al. (2025) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2025.3572032 · Cited by 10
“To improve gate control and guarantee electrostatic control in ultrashort channels, meeting the requirements of more advanced semiconductor processes, the gate-all-around field-effect transistor (GAAFET) has become a mainstream research device for the 3-nm and sub-3-nm nodes [6], [7].”
TCAD-Based Assessment of the Lateral GAA Nanosheet Transistor for Future CMOS
Huang, Y.-C., Chiang, M., Wang, S.-J., et al. (2021) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2021.3124472 · Cited by 10
Hu, R., & Yu, L. (2022) · Nanotechnology · doi:10.1088/1361-6528/ac547a · Cited by 10
Cheng, X., Li, Y., Wang, G., et al. (2020) · Semiconductor Science and Technology · doi:10.1088/1361-6641/abae3e · Cited by 10
Xie, L., Zhu, H., Zhang, Y., et al. (2021) · Nanomaterials · doi:10.3390/nano11061408 · Cited by 10
Metadata
- Authors
- Bae, G., Bae, D.-I., Kang, M., Hwang, S. M., Kim, S. S., Seo, B., Kwon, T. Y., Lee, T. J., Moon, C., Choi, Y. M., Oikawa, K., Masuoka, S., Chun, K. Y., Park, S. H., Shin, H. J., Kim, J. C., Bhuwalka, K. K., Kim, D. H., Kim, W. J., Yoo, J., Jeon, H. Y., Yang, M. S., Chung, S.-J., Kim, D., Ham, B. H., Park, K. J., Kim, W. D., Park, S. H., Song, G., Kim, Y. H., Kang, M. S., Hwang, K. H., Park, C.-H., Lee, J.-H., Kim, D.-W., Jung, S.-M., & Kang, H. K.
- Affiliations
- Samsung Electronics, Samsung R&D Center, Hwasung-City, Gyeonggi-Do, Republic of Korea
- Samsung (South Korea) (KR)
- ORCID
- Venue
- 2018 IEEE International Electron Devices Meeting (IEDM)
- Publisher
- IEEE
- Published
- 2018-12
- Pages
- 28.7.1-28.7.4
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W2913404074
- Cited by
- 368
- References
- 13
- Citations by year
- 2026: 38 · 2025: 83 · 2024: 64 · 2023: 52 · 2022: 53 · 2021: 38 · 2020: 27 · 2019: 13
- FWCI
- 31.10
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Technical digest - International Electron Devices Meeting/Technical digest (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Materials Science › Materials Chemistry › 2D Materials and Applications
- Keywords
- gate-all-around MOSFET, subthreshold swing, effective channel width, standard cell design, SRAM, device reliability, low power design, effective capacitance, effective resistance
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