The DOI matches its Crossref record; 2 of the 2 references it cites were found in a registry or an index.
16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips
Abstract
Recent SRAM-based computation-in-memory (CIM) macros enable mid-to-high precision multiply-and-accumulate (MAC) operations with improved energy efficiency using ultra-small/small capacity (0.4-8KB) memory devices. However, advanced CIM-based edge-AI chips favor multiple mid/large capacity SRAM-CIM macros: with high input (IN) and weight (W) precision to reduce the frequency of data reloads from external DRAM, and to avoid the need for additional SRAM buffers or ultra-large on-chip weight buffers. However, enlarging memory capacity and throughput increases the delay parasitics on WLs and BLs, and the number of parallel computing elements; resulting in longer compute latency (tAC), lower energy-efficiency (EF), degraded signal margin, and larger fluctuations in power consumption across data-patterns (see Fig. 16.3.1). Recent SRAM-CIM macros tend to not use in-lab SRAM cells, with a logic-based layout, in favor of foundry provided compact-layout 8T [2], 3, [5] or 6T cells with local-computing cells (LCCs) [4], [6] to reduce the cell-array area and facilitate manufacturing. This paper presents a SRAM-CIM structure using (1) a segmented-BL charge-sharing (SBCS) scheme for MAC operations, with low energy consumption and a consistently high signal margin across MAC values (MACV); (2) An new LCC cell, called a source-injection local-multiplication cell (SILMC), to support the SBCS scheme with a consistent signal margin against transistor process variation; and (3) A prioritized-hybrid-ADC (Ph-ADC) to achieve a small area and power overhead for analog readout. A 28nm 384kb SRAM-CIM macro was fabricated using a foundry compact-6T cell with support for MAC operations with 16 accumulations of 8b-inputs and 8b-weights with near-full precision output (20b). This macro achieves a 7.2ns tACand a 22.75TOPS/W EF for 8b-MAC operations with an FoM (IN-precision × W-precision × output-ratio × output-channel × EF/tAC) 6× higher than prior work.
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“Although several compute-in-memory or near-memory approaches based on SRAMs and digital compute35–38 have been presented in the literature, most of these do not address the energy and time costs of reloading weights, thus making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult.”
From An analog-AI chip for energy-efficient speech recognition and transcription (2023) · cites this paper as [38]
Citations
Cites
Biswas, A., & Chandrakasan, A. P. (2018) · 2018 IEEE International Solid - State Circuits Conference - (ISSCC) · doi:10.1109/isscc.2018.8310397 · Cited by 337
Su, J.-W., Si, X., Chou, Y.-C., Chang, T.-W., Huang, W.-H., Tu, Y.-N., Liu, R., Lu, P.-J., Liu, T.-W., Wang, J.-H., et al. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC) · doi:10.1109/isscc19947.2020.9062949 · Cited by 189
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Research works printed but not linked: 4
- 10.1109/ISSCC19947.2020.9062995 · DOI
- 10.1109/ISSCC.2019.8662392 · DOI
- 10.1109/ISSCC19947.2020.9062985 · DOI · Paper page
- 10.1109/ISSCC.2019.8662435 · DOI
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Sorted by citations
An analog-AI chip for energy-efficient speech recognition and transcription
Ambrogio, S., Narayanan, P., Okazaki, A., Fasoli, A., Mackin, C., Hosokawa, K., Nomura, A., Yasuda, T., Chen, A., Friz, A., et al. (2023) · Nature · doi:10.1038/s41586-023-06337-5 · Cited by 269
“Although several compute-in-memory or near-memory approaches based on SRAMs and digital compute 35–38 have been presented in the literature, most of these do not address the energy and time costs of reloading weights, thus making direct side-by-side comparisons against NVM-based weight-stationary…”
BackgroundMori, H., Zhao, W.-C., Lee, C.-E., Lee, C.-F., Hsu, Y.-H., Chuang, C., Hashizume, T., Tung, H.-C., Liu, Y.-Y., Wu, S.-R., et al. (2023) · IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42615.2023.10067555 · Cited by 130
“Recent work examined tradeoffs between MAC throughput, energy efficiency and accuracy for analog based CIM [1-3].”
BackgroundWu, P., Su, J.-W., Hong, L., Ren, J.-S., Chien, C.-H., Chen, H.-Y., Ke, C.-E., Hsiao, H.-M., Li, S.-H., Sheu, S.-S., et al. (2023) · IEEE International Solid-State Circuits Conference · doi:10.1109/isscc42615.2023.10067527 · Cited by 117
“This paper presents a true FP-IMC macro featuring (1) a hybrid-domain macro structure that enables computation of both the exponent and mantissa in an FP-MAC within the same IMC macro.”
BackgroundMethodInfluentialSelf-citationA 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks
Yu, C., Yoo, T., Chai, K. T. C., Kim, T. T.-H., & Kim, B. (2022) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2022.3162602 · Cited by 118
Tu, F., Wu, Z., Wang, Y., Liang, L., Liu, L., Ding, Y., Liu, L., Wei, S., Xie, Y., & Yin, S. (2022) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2022.3213542 · Cited by 102
“2) For Challenge1b , we design the CIM macro with a bitline-transpose structure to align the directions of input feeding and weight writing, instead of the previous wordline-feeding solutions [6], [15], [23].”
BackgroundMethodResultInfluential
Metadata
- Authors
- Su, J.-W., Chou, Y.-C., Liu, R., Liu, T.-W., Lu, P.-J., Wu, P.-C., Chung, Y.-L., Hung, L.-Y., Ren, J.-S., Pan, T., Li, S.-H., Chang, S.-C., Sheu, S.-S., Lo, W.-C., Wu, C.-I., Si, X., Lo, C.-C., Liu, R.-S., Hsieh, C.-C., Tang, K.-T., & Chang, M.-F.
- Affiliations
- National Tsing Hua University (TW)
- Industrial Technology Research Institute (TW)
- ORCID
- Venue
- 2021 IEEE International Solid-State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Published
- 2021-02-13
- Pages
- 250-252
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W3133754064
- Cited by
- 207
- References
- 0
- Citations by year
- 2026: 21 · 2025: 35 · 2024: 34 · 2023: 54 · 2022: 52 · 2021: 11
- FWCI
- 59.27
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
- Funders
- Nova
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Keywords
- in-memory computing, 6T SRAM, multiply-accumulate operations, energy efficiency, process variation, analog readout
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