Cited by 338Analog and Mixed-Signal Circuit DesignRadio Frequency Integrated Circuit DesignNeuroscience and Neural Engineering

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A 0.013 ${\hbox {mm}}^{2}$, 5 $\mu\hbox{W}$, DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

Muller, Rikky, Gambini, Simone, Rabaey, Jan M.·2012·IEEE Journal of Solid-State Circuits

DOI 10.1109/jssc.2011.2163552

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Abstract

We present an area-efficient neural signal-acquisition system that uses a digitally intensive architecture to reduce system area and enable operation from a 0.5 V supply. The architecture replaces ac coupling capacitors and analog filters with a dual mixed-signal servo loop, which allows simultaneous digitization of the action and local field potentials. A noise-efficient DAC topology and an compact, boxcar sampling ADC are used to cancel input offset and prevent noise folding while enabling “per-pixel” digitization, alleviating system-level complexity. Implemented in a 65 nm CMOS process, the prototype occupies 0.013 mm2while consuming 5 μW and achieving 4.9 μVrms of input-referred noise in a 10 kHz bandwidth.

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Show all 27 references

Research works printed but not linked: 2

xiao, 2010, A 20 <ref_formula><tex Notation="TeX">$\mu{W}$</tex> </ref_formula> neural recording tag with supply-current-modulated AFE in 0.13 <ref_formula> <tex Notation="TeX">$\mu{\hbox {m}}$</tex></ref_formula> CMOS, IEEE Solid-State Circuits Conf Dig Tech Papers, 122
muller, 2011, A 0.013 <ref_formula><tex Notation="TeX">${\hbox {mm}}^{2}$</tex></ref_formula>, 5 <ref_formula><tex Notation="TeX">$\mu{W}$</tex> </ref_formula>, DC-coupled neural signal acquisition IC with 0.5 V supply, IEEE Solid-State Circuits Conf Dig Tech Papers, 302

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Authors: Muller, R., Gambini, S., & Rabaey, J. M.
Affiliations: University of California, Berkeley (US)
ORCID: Muller, Rikky
Rabaey, Jan M.
Venue: IEEE Journal of Solid-State Circuits
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
Published: 2012-01
Volume: 47
Issue: 1
Pages: 232-243
ISSN: 0018-9200 (ISSN-L)
1558-173X
DOI: 10.1109/jssc.2011.2163552
OpenAlex: W2003444784
Cited by: 338
References: 27
Citations by year: 2026: 11 · 2025: 23 · 2024: 18 · 2023: 21 · 2022: 22 · 2021: 26 · 2020: 26 · 2019: 25 · 2018: 34 · 2017: 28 · 2016: 25 · 2015: 26 · 2014: 26 · 2013: 20 · 2012: 7
FWCI: 10.04
Type: journal article
Language: en
Open access: closed
Licence: ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html (vor)
Locations: IEEE Journal of Solid-State Circuits (publishedVersion)
Topics: Physical Sciences › Engineering › Electrical and Electronic Engineering › Analog and Mixed-Signal Circuit Design
Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
Life Sciences › Neuroscience › Cellular and Molecular Neuroscience › Neuroscience and Neural Engineering
Keywords: neural signal acquisition, low-power integrated circuits, local field potentials, digital-to-analog converter, noise folding, low-voltage operation, 65 nm CMOS, area-efficient circuit design

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A 0.013 ${\hbox {mm}}^{2}$, 5 $\mu\hbox{W}$, DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply

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