A 82-nW Chaotic Map True Random Number Generator Based on a Sub-Ranging SAR ADC
Abstract
An ultra-low power true random number generator (TRNG) based on a sub-ranging SAR analog-to-digital converter (ADC) is proposed. The proposed TRNG is composed of a coarse-SAR ADC with a low-power adaptive-reset comparator and a low-power dynamic amplifier. The coarse-ADC part is shared with a sub-ranging SAR ADC for area reduction. The shared coarse-ADC not only plays the role of discrete-time chaotic circuit but also reduces the overall SAR ADC energy consumption by selectively activating the fine-SAR ADC. Also, the proposed dynamic residue amplifier consumes only 48 nW and the adaptive-reset comparator generates a chaotic map with only 6-nW consumption. The proposed TRNG core occupies 0.0045 mm2in 0.18-μm CMOS technology and consumes 82 nW at 270-kbps throughput with 0.6-V supply. It successfully passes all of National Institute of Standards and Technology (NIST) tests, and it achieves the state-of-the-art figure-of-merit of 0.3 pJ/bit.
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Si-CMOS-based tRNGs use circuitry with various types of entropy sources, such as timing jitter, chaotic maps, metastability, or noise jitter from SRAM bit-line leakages, for low power consumption.
“In contrast, Si-CMOS–based tRNGs use circuitry that uses various types of entropy sources, such as timing jitter, chaotic maps, metastability, or noise jitter from SRAM bit-line leakages for low power consumption.”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [20]
Si-CMOS-based tRNGs show excellent randomness and insensitivity to fabrication-induced variability.
“They show excellent randomness and insensitivity to fabrication-induced variability.”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [20]
Those entropy sources rely on operation-induced variations.
“Note that those entropy sources rely on operation-induced variations (19–23).”
From Cryptographic transistor for true random number generator with low power consumption (2024) · cites this paper as [20]
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Taneja, S., Rajanna, V. K., & Alioto, M. (2021) · 2021 IEEE International Solid-State Circuits Conference (ISSCC) · doi:10.1109/isscc42613.2021.9366019 · Cited by 58 · see citing works
Cryptographic transistor for true random number generator with low power consumption
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“Kim et al. ( 20 ) demonstrated a circuit-based tRNG using residual voltage in an ADC.”
Self-citation
- Authors
- Kim, M., Ha, U., Lee, K. J., Lee, Y., & Yoo, H.-J.
- Affiliations
- Korea Advanced Institute of Science and Technology (KR)
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 2017-07
- Volume
- 52
- Issue
- 7
- Pages
- 1953-1965
- ISSN
- 0018-9200 (ISSN-L)
- 1558-173X
- OpenAlex
- W2610291885
- Cited by
- 97
- References
- 36
- Citations by year
- 2026: 3 · 2025: 16 · 2024: 9 · 2023: 11 · 2022: 9 · 2021: 16 · 2020: 12 · 2019: 12 · 2018: 9
- FWCI
- 4.07
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Journal of Solid-State Circuits (publishedVersion)
- Scholarworks@UNIST (Ulsan National Institute of Science and Technology) (submittedVersion)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Physical Sciences › Computer Science › Hardware and Architecture › Physical Unclonable Functions (PUFs) and Hardware Security
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Keywords
- true random number generator, chaotic maps, ultra-low power, energy efficiency, NIST randomness tests, 0.18 μm CMOS
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