A Low-Power 32-Channel Digitally Programmable Neural Recording Integrated Circuit
Abstract
We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. The chip consists of eight neural recording modules where each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier's input-referred noise to suit the background noise at the recording site. The amplifier's input-referred noise can be adjusted from 11.2 μVrms (total power of 5.4 μW) down to 5.4 μVrms (total power of 20 μW) in the spike-recording setting. The ADC in each recording module digitizes the a.c. signal input to each amplifier at 8-bit precision with a sampling rate of 31.25 kS/s per channel, with an average power consumption of 483 nW per channel, and, because of a.c. coupling, allows d.c. operation over a wide dynamic range. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications. The presented chip was successfully tested in an in vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 μ W. The neural amplifier and the ADC occupy areas of 0.03 mm(2) and 0.02 mm(2) respectively, making our design simultaneously a…
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Another power-scheduling method is to adapt each amplifier channel's current consumption according to the background noise at its respective electrode.
“Therefore, another power-scheduling method is to adapt the current consumption of each amplifier channel according to the background noise present at the respective electrode [17, 122, 141].”
From Implantable neurotechnologies: a review of integrated circuit neural amplifiers (2016) · cites this paper as [141]
The folded cascode OTA is the natural choice for front-end amplifiers operating below 3 V and requiring low NEF and PEF values.
“Instead, the folded cascode OTA (Fig. 5d) is the natural choice for front-end amplifiers operating at supply voltages below 3 V and requiring low NEF and PEF values [103, 141, 142].”
From Implantable neurotechnologies: a review of integrated circuit neural amplifiers (2016) · cites this paper as [141]
Wattanapanitch et al. proposed an NEF optimization scheme for low-voltage neural amplifiers using the folded cascode OTA, which was adopted in later studies.
“Wattanapanitch et al. [142] further proposed an NEF optimization scheme for low-voltage neural amplifiers implemented using the folded cascode OTA, which were adopted in later studies [103, 141].”
From Implantable neurotechnologies: a review of integrated circuit neural amplifiers (2016) · cites this paper as [141]
Recent works reported that careful design of the OTA A1 makes low current consumption and low input-referred noise easily achievable.
“Recent works have also reported that by carefully designing the OTA A1, low current consumption and low input-referred noise are easily achievable [63, 141, 142, 156].”
From Implantable neurotechnologies: a review of integrated circuit neural amplifiers (2016) · cites this paper as [141]
Wattanapanitch and Sarpeshkar partitioned an IC neural amplifier into two voltage domains, with front-end amplifiers at 1.8 V and the ADC and backend digital blocks at 1 V to reduce dynamic switching power.
“For example, the IC neural amplifier reported by Wattanapanitch and Sarpeshkar [141] was partitioned into two separate voltage domains. The front-end amplifiers operated at 1.8 V, while the supply voltage of the ADC and the backend digital blocks were reduced to 1 V to decrease the dynamic switching power.”
From Implantable neurotechnologies: a review of integrated circuit neural amplifiers (2016) · cites this paper as [141]
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- Authors
- Wattanapanitch, W., & Sarpeshkar, R.
- Affiliations
- Kasetsart University (TH)
- Massachusetts Institute of Technology (US)
- Venue
- IEEE Transactions on Biomedical Circuits and Systems
- Published
- 2011-12
- Volume
- 5
- Issue
- 6
- Pages
- 592-602
- ISSN
- 1932-4545 (ISSN-L)
- 1940-9990
- OpenAlex
- W2061752509
- Cited by
- 146
- References
- 31
- Citations by year
- 2025: 3 · 2024: 5 · 2023: 4 · 2022: 6 · 2021: 8 · 2020: 3 · 2019: 12 · 2018: 10 · 2017: 14 · 2016: 10 · 2015: 23 · 2014: 19 · 2013: 21 · 2012: 8
- FWCI
- 9.09
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Transactions on Biomedical Circuits and Systems (publishedVersion)
- PubMed (publishedVersion)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Keywords
- neural amplifier, adaptive biasing, input-referred noise, spike recording, local field potentials, analog-to-digital converter, energy-efficient ADC, CMOS
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