The DOI matches its Crossref record; 50 of the 50 references it cites were found in a registry or an index; none of the 1 sources its claims cite is checked for support yet.
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference
Open accessAbstract
A multicore analogue in-memory computing chip that is designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory can be used for deep neural network inference. Analogue in-memory computing (AIMC) with resistive memory devices could reduce the latency and energy consumption of deep neural network inference tasks by directly performing computations within memory. However, to achieve end-to-end improvements in latency and energy consumption, AIMC must be combined with on-chip digital operations and on-chip communication. Here we report a multicore AIMC chip designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory. The fully integrated chip features 64 AIMC cores interconnected via an on-chip communication network. It also implements the digital activation functions and additional processing involved in individual convolutional layers and long short-term memory units. With this approach, we demonstrate near-software-equivalent inference accuracy with ResNet and long short-term memory networks, while implementing all the computations associated with the weight layers and the activation functions on the chip. For 8-bit input/output matrix–vector multiplications, in the four-phase (high-precision) or one-phase (low-precision) operational read mode, the chip can achieve a maximum throughput of 16.1 or 63.1 tera-operations per second at an energy efficiency of 2.48 or 9.76 tera-operations per second per watt, respectively.
Overview
AI snapshot
Written from a shortened version of the paper’s full text (it is longer than we read).
TL;DR
Hermes is a 64-core analog in-memory compute chip in 14-nm CMOS with backend-integrated phase-change memory, designed to run deep neural network inference with on-chip digital operations and communication. It demonstrates near software-equivalent accuracy on ResNet and LSTM tasks while achieving 63.1 TOPS and 9.76 TOPS W−1 for 8-bit input/output matrix-vector multiplications.
Key findings
- The chip contains 64 cores, each with a 256×256 PCM crossbar, enabling up to 4,194,304 weights on-chip; it is fabricated in 14-nm CMOS, measures 12 mm × 12 mm, and uses 418 communication links implementing a 5 Parallel Prism topology.
- On 63 of 64 cores, more than 99% of unit cells can be programmed to |G_RESET| smaller than 5 ADC counts and G_SET larger than 50 ADC counts; the outlier core has 98.4% yield. One-device-per-weight (ODP) programming achieves precision close to 3-bit weights, while two-device-per-weight (TDP) achieves between 3-bit and 4-bit weights.
- For ResNet-9 on CIFAR-10, Hermes achieves 92.81% accuracy with TDP and 92.23% with ODP, versus a software baseline of 93.67%; digital quantization adds another 0.2–0.3% drop. The chip reaches a maximal throughput of 63.1 TOPS at 9.76 TOPS W−1 for 8-bit input/output MVMs, with MVM throughput per area >15× higher than comparable multi-core resistive-memory AIMC chips.
- The paper reports near software-equivalent inference accuracy for ResNet and LSTM networks, including CIFAR-10 image recognition, Penn Treebank character prediction, and Flickr8k image caption generation, with all weight-layer computations and activation functions performed on-chip.
Methods
- The chip integrates 64 AIMC cores with backend PCM, per-row current-controlled oscillator ADCs, local digital processing units (LDPUs), global digital processing units (GDPUs), and link controllers. Each unit cell uses four PCM devices (two per polarity).
- MVM accuracy was characterized across all 64 cores using uniformly distributed 30% sparse weight matrices and 2,048 input vectors; errors were decomposed into total, linear (weight programming), and residual contributions. Two closed-loop iterative programming algorithms, ODP and TDP, were compared.
- DNN inference used hardware-aware training with noise injection on synaptic weights via the IBM Analog Hardware Acceleration Kit. Trained weights were mapped to conductances; ResNet-9, PTB LSTM, and Flickr8k LSTM networks were run with on-chip MVMs, activation functions, batch normalization, LSTM cell-state computation, aggregation, bias addition, and affine scaling. Max-pooling and embeddings were performed in software.
Limitations
- The paper states that max-pooling in ResNet-9 and character/image/word embedding in the LSTM networks are not supported by the chip and are performed in software.
- The paper states that PCM conductance drift causes linear and total MVM error to increase over time; TDP shows noticeable residual error due to sampling a wider, more nonlinear ADC range and higher leakage from non-RESET devices.
- Evident from the provided text: the excerpt is truncated before the full PTB and Flickr8k accuracy results, so those specific numbers cannot be summarized here.
Model-written summary. Check it against the paper before relying on it.
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Claims the paper makes
7 No basis given · 5 Own result · 2 Own interpretation · 1 Not checked yet
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“while achieving the highest accuracy on the CIFAR-10 benchmark.”
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In the paper
“The yield of the remaining outlier core is 98.4%.”
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“The fully-integrated chip features 64 256x256 AIMC cores interconnected via an on-chip communication network.”
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“With TDP, a precision between 3-bit and 4-bit weights is achieved.”
plaindirect- Asserted: passes — The authors put it forward as true.
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- Load-bearing: passes — The paper’s conclusions depend on it.
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A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“When using TDP, ε linear is significantly reduced compared with ODP”
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“software baseline of 93.67%”
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In the paper
“The biggest accuracy drop from the software baseline comes from the weight error”
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In the paper
“which is less than 1% below the software baseline of 93.67%”
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In the paper
“We attribute this reduction to a higher signal-to-noise ratio achieved when using two devices instead of one20.”
What the sources say
- Not checked yetcites [20] Khwa, W.-S. et al. A 40-nm, 2M-cell, 8b-precision, hybrid SLC-MLC PCM computing-in-memory macro with 20.5–65.0TOPS/W for tiny-Al edge devices. in 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1–3 (IEEE, 2022). source
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In the paper
“showing that the weight programming error is effectively lowered when using more devices per weight.”
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- Probably not a substantial claim. 2
- It may state two separate claims as one. 3
The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“The LSTM network for PTB character prediction (1,299,312 weights and 2,066 biases)”
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Probably not a substantial claim. The paper’s conclusions may not depend on it.
The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“ε linear and thus also ε total increase over time as shown in Fig. 2d.”
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“It also implements the digital activation functions and processing involved in ResNet convolutional neural networks and long short-term memory (LSTM) networks.”
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“The custom ResNet-9 network (1,866,536 synaptic weights and 10 biases)”
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Probably not a substantial claim. The paper’s conclusions may not depend on it.
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“The chip can achieve a maximal throughput of 63.1 TOPS at an energy efficiency of 9.76 TOPS W−1 for 8-bit input/output matrix-vector multiplications.”
plain- Asserted: passes — The authors put it forward as true.
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Claims other papers make about this one
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The source backs part of the claim, not all of it — or backs it for a different population, condition or comparison.
In the citing paper
“The most advanced studies in this field have reported fully integrated memristor-based compute-in-memory systems48,53–55,58,59,61,71–73, but a systematic description of essential details on the device structure or circuit architecture are generally lacking in these reports.”
From Hardware implementation of memristor-based artificial neural networks (2024) · cites this paper as [73]
Experimental — accuracy not yet measuredThe source backs part of the claim, not all of it — or backs it for a different population, condition or comparison.
In the citing paper
“For instance in a recent study54, a ResNet9 CNN was trained with a similar general HWA training approach yielding vastly improved AIMC accuracy in hardware.”
From Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (2023) · cites this paper as [54]
Experimental — accuracy not yet measuredThe source backs part of the claim, not all of it — or backs it for a different population, condition or comparison.
In the citing paper
“It has been already verified in hardware, however, that HWA training using noise injection is very effective at improving the robustness for selected (smaller) DNNs.”
From Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (2023) · cites this paper as [54]
Experimental — accuracy not yet measured
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Memristor-based feature learning for pattern classification
Shi, T., Gao, L., Tian, Y., Tang, S., Liu, J., Li, Y., Zhou, R., Cui, S., Zhang, H., Li, Y., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-56286-y · Cited by 38
“To make the network training process be aware of hardware non-idealities, the imprecision-based neural network training framework incorporates limited device conductance range, output noise and device failure in network training (detailed in Supplementary Notes) 41 .”
InfluentialNeural architecture search for in-memory computing-based deep learning accelerators
Krestinskaya, O., Fouda, M. E., Benmeziane, H., Maghraoui, K. E., Sebastian, A., Lu, W. D., Lanza, M., Li, H. H., Kurdahi, F. J., Fahmy, S. A., et al. (2024) · Nature Reviews Electrical Engineering · doi:10.1038/s44287-024-00052-7 · Cited by 35
Self-citationPhase-Change Memory from Molecular Tellurides
Schenk, F. M., Zellweger, T., Kumaar, D., Bošković, D., Wintersteller, S., Solokha, P., NEGRI, S. D., Emboras, A., Wood, V. C., & Yarema, M. (2023) · ACS Nano · doi:10.1021/acsnano.3c10312 · Cited by 33
Guo, Z., Zhang, J., Wang, J., Liu, X., Guo, P., Sun, T., Li, L., Gao, H., Xiong, L., & Huang, J. D. (2024) · Nano Letters · doi:10.1021/acs.nanolett.4c01606 · Cited by 33
Rapid learning with phase-change memory-based in-memory computing through learning-to-learn
Ortner, T., Petschenig, H., Vasilopoulos, A., Renner, R., Brglez, Š., Limbacher, T., Piñero-Fuentes, E., Linares-Barranco, A., Pantazi, A., & Legenstein, R. A. (2025) · Nature Communications · doi:10.1038/s41467-025-56345-4 · Cited by 35
Self-citationProbabilistic photonic computing with chaotic light
Brückerhoff‐Plückelmann, F., Borras, H., Klein, B., Varri, A., Becker, M., Dijkstra, J., Brückerhoff, M., Wright, C. D., Salinga, M., Bhaskaran, H., et al. (2024) · Nature Communications · doi:10.1038/s41467-024-54931-6 · Cited by 40
“In this case, sampling from the posterior distribution is implemented by reading, and potentially rewriting, the memristor several times while the neuromorphic crossbar architecture ensures the efficient evaluation of the model 22 .”
The potential of multidimensional photonic computing
Bente, I., Taheriniya, S., Lenzini, F., Brückerhoff‐Plückelmann, F., Kues, M., Bhaskaran, H., Wright, C. D., & Pernice, W. H. P. (2025) · Nature Reviews Physics · doi:10.1038/s42254-025-00843-3 · Cited by 36
Multilevel Ferroelectric Domain Wall Memory for Neuromorphic Computing
Shen, B., Sun, H., Hu, X., Sun, J., Jiang, J. F., Zhang, Z., & Jiang, A. (2024) · Advanced Functional Materials · doi:10.1002/adfm.202315954 · Cited by 29
Yue, W., Wu, K., Li, Z., Zhou, J., Wang, Z., Zhang, T., Yang, Y., Ye, L., Wu, Y., Bu, W., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-56412-w · Cited by 30
A neuromorphic processor with on-chip learning for beyond-CMOS device integration
Greatorex, H., Richter, O., Mastella, M., Cotteret, M., Klein, P., Fabre, M., Rubino, A., Girão, W. S., Chen, J.-R., Ziegler, M., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-61576-6 · Cited by 34
Deployment of Artificial Intelligence Models on Edge Devices: A Tutorial Brief
Żyliński, M., Nassibi, A., Rakhmatulin, I., Malik, A., Papavassiliou, C., & Mandic, D. P. (2023) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2023.3336831 · Cited by 27
“Additionally, their latest advancements include a 64-core mixed-signal in-memory chip [54], which can achieve an impressive throughput of 63.1 Tera operations per second and an energy efficiency of 9.76 Tera operations per second per Watt, particularly in the low-precision mode.”
BackgroundInfluentialAn Analysis of Components and Enhancement Strategies for Advancing Memristive Neural Networks
Park, H., Han, J., Yim, S., Shin, D. H., Park, T. W., Woo, K. S., Lee, S. H., Cho, J. M., Kim, H. W., Park, T., et al. (2025) · Advanced Materials · doi:10.1002/adma.202412549 · Cited by 27
A full-stack memristor-based computation-in-memory system with software-hardware co-development
Yu, R., Wang, Z., Liu, Q., Gao, B., Hao, Z., Guo, T., Ding, S., Zhang, J., Qin, Q., Wu, D. M., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-57183-0 · Cited by 33
“The cells exhibit excellent programming precision and retention time for both 3-bit single cell and 4-bit grouped cells (see Supplementary Note 2).”
InfluentialA near-threshold memristive computing-in-memory engine for edge intelligence
Wang, L., Li, W., Zhou, Z., An, J., Ye, W., Li, Z., Gao, H., Hu, H., Liu, J., Chen, X., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-61025-4 · Cited by 29
“Previous works have investigated the model-to-hardware mapping strategies and the data fl ow control for multi-macro systems 23,41,57,58 .”
Generative complex networks within a dynamic memristor with intrinsic variability
Guo, Y., Duan, W., Liu, X., Wang, X., Wang, L., Duan, S., Ma, C., & Li, H. (2023) · Nature Communications · doi:10.1038/s41467-023-41921-3 · Cited by 30
“…by the classical DL practice, these memristive systems have been built primarily as the accelerators for fi xed-architecture ANN algorithms 10 – 17 which in turn demand memristive devices to be static (because typical ANN models are static) and have strictly reproducible behaviors (because…”
A dual-domain compute-in-memory system for general neural network inference
Wang, Z., Yu, R., Jia, Z., He, Z., Yang, T., Gao, B., Li, Y., Hu, Z., Hao, Z., Liu, Y., et al. (2025) · Nature Electronics · doi:10.1038/s41928-024-01315-9 · Cited by 30
“We considered a commonly reported 256 × 256 ACIM array 2,3,12,26,27 .”
Yang, J., Mao, R., Jiang, M., Cheng, Y., Sun, P.-S. V., Dong, S., Pedretti, G., Sheng, X., Ignowski, J., Li, H., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-56254-6 · Cited by 28
Radiofrequency signal processing with a memristive system-on-a-chip
Huang, Y., He, C., Ling, Y., Ge, N., Yang, J. J., Hu, M., Katehi, L. P. B., & Xia, Q. (2025) · Nature Electronics · doi:10.1038/s41928-025-01409-y · Cited by 26
“…signal processing scenario, where transmitter identification is achieved using identifier (ID) information circuit and architecture level, the integration of multiple memristive crossbar arrays into a single chip with essential peripheral circuits 10–12 has expanded the overall capability of AIMC.”
Zhu, Y. J., Luo, M., Hua, X., Xu, L., Lei, M., Liu, M., Liu, J., Liu, Y., Wang, Q., Yang, C., et al. (2024) · Optica · doi:10.1364/optica.514341 · Cited by 25
Bhatnagar, V., & Kumar, A. (2025) · Energy Storage · doi:10.1002/est2.70272 · Cited by 23
Deaville, P., Zhang, B., & Verma, N. (2024) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2024.3386462 · Cited by 21
“IMC based on embedded non-volatile memory (eNVM), such as resistive RAM (ReRAM) [6], MRAM [7], and phase-change memory (PCM) [8], [9], has been of high interest due to bit-cell density scalability and low-leakage retention for low-power edge applications.”
BackgroundMethodMemristor-based adaptive analog-to-digital conversion for efficient and accurate compute-in-memory
Hong, H., Du, Z., Jiang, M., Mao, R., Ren, Y., Li, F., Mao, W., Peng, M., Zhang, W., Liu, Z., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-65233-w · Cited by 27
“Whilethisworkfocuses on optimizing the quantization stage, our ADC can operate synergistically with advanced techniques that address circuit-level non-idealities, such as signal margin limitations 50 and IR drop 51 , as well as crossbar device-to-device variations 17,52,53 .”
Beyond multilayer perceptrons: Investigating complex topologies in neural networks
Boccato, T., Ferrante, M., Duggento, A., & Toschi, N. (2023) · Neural Networks · doi:10.1016/j.neunet.2023.12.012 · Cited by 26
Local prediction-learning in high-dimensional spaces enables neural networks to plan
Stöckl, C., Yang, Y., & Maass, W. (2024) · Nature Communications · doi:10.1038/s41467-024-46586-0 · Cited by 26
Current opinions on memristor-accelerated machine learning hardware
Jiang, M., Xu, Y., Li, Z., & Li, C. (2025) · Current Opinion in Solid State and Materials Science · doi:10.1016/j.cossms.2025.101226 · Cited by 20
Antolini, A., Zavalloni, F., Lico, A., Quqa, S., Greco, L., Mangia, M., Pareschi, F., Pasotti, M., & Scarselli, E. F. (2025) · Sensors · doi:10.3390/s25123618 · Cited by 19
Falcone, D. F., Clerico, V., Choi, W., Stecconi, T., Horst, F., Bégon‐Lours, L., Galetta, M., Porta, A. L., Garg, N., Alibart, F., et al. (2025) · Advanced Functional Materials · doi:10.1002/adfm.202504688 · Cited by 18
Vasilopoulos, A., Büchel, J., Kersting, B., Lammie, C., Brew, K. W., Choi, S., Philip, T. M., Saulnier, N., Narayanan, V., Gallo, M. L., et al. (2023) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2023.3321014 · Cited by 19
“An estimate of the programed weights, ˆ W , can be inferred through MVM operations [26] by solving the following equation : (2) Fig.”
BackgroundSelf-citationNeuromorphic one-shot learning utilizing a phase-transition material
Galloni, A. R., Yuan, Y., Zhu, M., Yu, H., Bisht, R. S., Wu, C. M., Grienberger, C., Ramanathan, S., & Milstein, A. D. (2024) · Proceedings of the National Academy of Sciences · doi:10.1073/pnas.2318362121 · Cited by 17
AI computing reaches for the edge
Iyer, S. S., & Roychowdhury, V. (2023) · Science · doi:10.1126/science.adk6874 · Cited by 17
Safe, secure and trustworthy compute-in-memory accelerators
Wang, Z., Wu, Y., Park, Y., & Lu, W. D. (2024) · Nature Electronics · doi:10.1038/s41928-024-01312-y · Cited by 16
“Similar to RRAM, prototype CIM systems based on PCM devices have been used for convolutional and fully connected neural networks 15,52 , recurrent neural networks 53 , hyperdimensional computing 54 and reservoir computing 55 , among other applications.”
Towards scalable memristive hardware for spiking neural networks
Chen, P., Zhang, B., He, E., Xiao, Y., Liu, F., Lin, P., Wang, Z., & Pan, G. (2025) · Materials Horizons · doi:10.1039/d4mh01676a · Cited by 19
Giacomo, S. D., Ronchi, M., Borghi, G., Schaart, D. R., Carminati, M., & Fiorini, C. E. (2024) · IEEE Transactions on Radiation and Plasma Medical Sciences · doi:10.1109/trpms.2024.3378421 · Cited by 16
“The proposed ASIC falls in the category of analog accelerator for IMC [82].”
BackgroundBoniardi, M., Baldo, M., Allegra, M., & Redaelli, A. (2024) · Advanced Electronic Materials · doi:10.1002/aelm.202400599 · Cited by 19
Heterogeneous Embedded Neural Processing Units Utilizing PCM-Based Analog In-Memory Computing
Boybat, I., Boesch, T., Allegra, M., Baldo, M., Agnoletto, J. J. B., Burr, G. W., Buschini, A., Cabrini, A., Calvetti, E., Cappetta, C., et al. (2024) · Technical digest - International Electron Devices Meeting/Technical digest · doi:10.1109/iedm50854.2024.10873479 · Cited by 16
Self-citationHow to Keep Pushing ML Accelerator Performance? Know Your Rooflines!
Verhelst, M., Luca Benini, C., & Verma, N. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3553765 · Cited by 17
“…SRAM [44], flash [46], resistive random access memory (ReRAM) [55], magnetic random access memory (MRAM) [52], [59], and phase-change memory (PCM) [60] have all shown that the bit-cell current variation and nonlinearity introduce substantial SNR and model-accuracy degradation, preventing scaling…”
Zhou, Y., du Toit, D. F. T., Elliott, S. R., Zhang, W., & Deringer, V. L. (2025) · Nature Communications · doi:10.1038/s41467-025-63732-4 · Cited by 20
“Some additional discussions in the last part of the manuscript could be very useful to the readers who will study their own materials systems.”
AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computing
Benmeziane, H., Lammie, C., Boybat, I., Rasch, M. J., Gallo, M. L., Tsai, H.-Y. S., Muralidhar, R., Niar, S., Ouarnoughi, H., Narayanan, V., et al. (2023) · IEEE International Conference on Edge Computing and Communications (EDGE) · doi:10.1109/edge60047.2023.00045 · Cited by 15
“Each core comprises a crossbar array of 256x256 PCM-based unit-cells along with a local digital processing unit [45].”
MethodInfluentialSelf-citationFalcone, D. F., Menzel, S., Stecconi, T., Galetta, M., Porta, A. L., Offrein, B. J., & Bragaglia, V. (2024) · Nanoscale Horizons · doi:10.1039/d4nh00072b · Cited by 15
Prospects and challenges of electrochemical random-access memory for deep-learning accelerators
Cui, J., Liu, H., & Cao, Q. (2024) · Current Opinion in Solid State and Materials Science · doi:10.1016/j.cossms.2024.101187 · Cited by 15
“The size of the ECRAM matrix has recently been increased to a 10 × 10 array programmed using the half-bias selection method [164], and it is expected to gradually catch up with or even exceed what have been demonstrated with RRAM or PCM [29,30].”
InfluentialDifferential Phase Change Memory (PCM) Cell for Drift-Compensated In-Memory Computing
Pistolesi, L., Ravelli, L., Glukhov, A., Herranz, A. D. G., López-Vallejo, M., Carissimi, M., Pasotti, M., Rolandi, P. L., Redaelli, A., Martín, I., et al. (2024) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2024.3480898 · Cited by 16
“PCM-based IMC has been already demonstrated as a suitable candidate for high-density, energy-efficient AI accelerators [4], [5], [6], [7], [8].”
Khan, A. A., Farzaneh, H., Friebel, K. F. A., Fournier, C., Chelini, L., & Castrillón, J. (2024) · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · doi:10.1145/3622781.3674189 · Cited by 21
“Even though various companies currently provide CIM and CNM systems for machine learning and other application domains (such as Axelera, d-Matrix, Sythara, UPMEM, etc.), their programmability remains a significant challenge.”
Zhuge, Y., Ren, Z., Xiao, Z., Zhang, Z., Liu, X., Liu, W., Xu, S., Ho, C. P., Li, N., & Lee, C. (2025) · Advanced Science · doi:10.1002/advs.202500525 · Cited by 14
Solution-based manufacturing of 2D materials for memristive device applications
Nam, K., Kim, G. Y., Rhee, D., Park, H., Jariwala, D., & Kang, J. (2025) · International Journal of Extreme Manufacturing · doi:10.1088/2631-7990/add634 · Cited by 15
Technology Roadmap of Bioinspired Computing Hardware
Wang, S., Li, Z., Pei, M., Ren, Q., Deng, M., Kah-Wee, A., Ascoli, A., Banerjee, S., Bonnin, M., van de Burgt, Y., et al. (2026) · ACS Nano · doi:10.1021/acsnano.5c17087 · Cited by 16
Progress and challenges of phase change memory for in-memory computing
Su, X., Guo, Z., Zhang, G., Tsai, H.-Y. S., & Li, N. (2025) · Current Opinion in Solid State and Materials Science · doi:10.1016/j.cossms.2025.101225 · Cited by 14
Driving for More Moore on Computing Devices with Advanced Non-Volatile Memory Technology
Wong, H., Li, W., Zhang, J., Bao, W., Wu, L., & Liu, J. (2025) · Electronics · doi:10.3390/electronics14173456 · Cited by 13
Analogue speech recognition based on physical computing
Zolfagharinejad, M., Büchel, J., Cassola, L., Kinge, S., Sarwat, S. G., Sebastian, A., & van der Wiel, W. G. (2025) · Nature · doi:10.1038/s41586-025-09501-1 · Cited by 13
“Second, for the classification based on the extracted features, we implement a CNN on an analogue in-memory computing (AIMC) 5 chip.”
InfluentialSelf-citationThe design of analogue in-memory computing tiles
Singh, A., Gallo, M. L., Vasilopoulos, A., Luquin, J., Narayanan, P., Burr, G. W., & Sebastian, A. (2025) · Nature Electronics · doi:10.1038/s41928-025-01537-5 · Cited by 15
Self-citationEnergy-Efficient Integrated Electro-Optic Memristors
He, Y., Farmakidis, N., Aggarwal, S., Dong, B., Lee, J. S., Wang, M., Zhang, Y., Parmigiani, F. R., & Bhaskaran, H. (2024) · Nano Letters · doi:10.1021/acs.nanolett.4c04567 · Cited by 13
The inherent adversarial robustness of analog in-memory computing
Lammie, C., Büchel, J., Vasilopoulos, A., Gallo, M. L., & Sebastian, A. (2024) · Nature Communications · doi:10.1038/s41467-025-56595-2 · Cited by 17
“This is typically referred to as programming noise 29 .”
Self-citationA lossless and fully parallel spintronic compute-in-memory macro for artificial intelligence chips
Li, H., Chai, Z., Dong, W.-K., He, J., Peng, R., Li, S., Kong, Z., Yuan, X., Wang, X., Yang, Z., et al. (2025) · Nature Electronics · doi:10.1038/s41928-025-01479-y · Cited by 16
“The measured MVM throughput per storage of 69.1 GOPS kb −1 is more than 17 times higher than a 64-core mixed-signal nvCIM chip 22 based on phase-change memory.”
InfluentialYoon, H., Park, S., Kim, Y. K., Baek, J., Kim, K. H., Yun, S., Son, H., Choi, J.-H., Jang, B. C., & Kang, D. (2025) · Advanced Functional Materials · doi:10.1002/adfm.202519498 · Cited by 12
AI-enabled flexible electronic systems via near-sensor and in-sensor computing
Xu, Z., Xie, E., Hou, C., Bai, Y., He, W., Liu, X., Zhang, F., & Huang, Y. (2026) · npj Flexible Electronics · doi:10.1038/s41528-026-00544-6 · Cited by 15
Büchel, J., Vasilopoulos, A., Kersting, B., Lammie, C., Brew, K. W., Philip, T. M., Saulnier, N., Narayanan, V., Gallo, M. L., & Sebastian, A. (2023) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2023.3329449 · Cited by 12
“Although all of these sources contribute to increasing the MVM error, the dominant contributor is conductance programming error [8].”
BackgroundSelf-citationFrom materials to applications: a review of research on artificial olfactory memory
Guo, L., Han, H., Du, C., Ji, X., Dai, M., Dosta, S., Zhou, Y., & Zhang, C. (2024) · Materials Horizons · doi:10.1039/d4mh01348d · Cited by 12
Wang, G., Shen, J., He, Y., Zhou, H., Huang, W., Wang, H., Cheng, Z., & Zhou, P. (2025) · Advanced Materials · doi:10.1002/adma.202419444 · Cited by 12
Probabilistic photonic computing for AI
Brückerhoff‐Plückelmann, F., Ovvyan, A. P., Varri, A., Borras, H., Klein, B., Meyer, L., Wright, C. D., Bhaskaran, H., Sarwat, S. G., Sebastian, A., et al. (2025) · Nature Computational Science · doi:10.1038/s43588-025-00800-1 · Cited by 16
“In particular, neuromorphic architectures leverage massively parallel in-memory computation, which offers a promising route to reducing the latency and power consumption of AI accelerators 5 .”
InfluentialSelf-citationMemcapacitors in neuromorphic architectures: the mechanisms, challenges, and applications
Chen, K., Shih, L., Chen, Y.-C., Lin, K., & Chen, J. (2025) · Journal of Materials Chemistry C · doi:10.1039/d5tc00993f · Cited by 11
Design of Analog-AI Hardware Accelerators for Transformer-based Language Models (Invited)
Burr, G. W., Tsai, H.-Y. S., Simon, W., Boybat, I., Ambrogio, S., Ho, C.-E., Liou, Z.-W., Rasch, M. J., Büchel, J., Narayanan, P., et al. (2023) · Technical digest - International Electron Devices Meeting/Technical digest · doi:10.1109/iedm45741.2023.10413767 · Cited by 13
“On a second chip, we integrated CCO-based ADCs (one per integration-row) into PCM-based CIM-Tiles [21] ( Fig.”
MethodSelf-citationDeaville, P., Zhang, B., & Verma, N. (2024) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2024.3512360 · Cited by 11
“…implementation of multiplication, compared with other works implementing signed multiplication using differential positive and negative pathways [16], which introduces another current path while still requiring additional area, or comparison with a reference resistance/column [26] which may…”
Random resistive memory-based deep extreme point learning machine for unified visual processing
Wang, S., Gao, Y., Li, Y., Zhang, W., Yu, Y., Wang, B., Lin, N., Chen, H., Zhang, Y., Jiang, Y., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-56079-3 · Cited by 12
Kwak, H., Choi, J., Han, S., Kim, E. H., Kim, C. H., Solomon, P. M., Lee, J.-Y., Kim, D., Shin, B., Lee, D., et al. (2025) · Nature Communications · doi:10.1038/s41467-025-58004-0 · Cited by 12
“In particular, if the vulnerability to variation and noise in analog signals remains unresolved, the advantage of analog AI computation will ultimately be limited to the application working with limited accuracies such as approximation 7,8 .”
Li, K., Zhang, J., Chen, Y., Pan, J., Zheng, Y., Xu, S., Zhao, R., Li, M., Qi, R., Huang, R. T., et al. (2025) · Science Advances · doi:10.1126/sciadv.adw8513 · Cited by 11
“Various types of memristors have been explored for artificial synapse applications, such as phase change memory ( 13 , 14 ), ferroelectric random access memory ( 15 – 17 ), magnetoresistive random access memory ( 18 ), and resistive random access memory (RRAM) ( 19 ).”
Duan, C., Yang, J., He, X., Qi, Y., Wang, Y., Wang, Y., He, Z., Yan, B., Wang, X., Jia, X., et al. (2023) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2023.3330819 · Cited by 10
“Table II presents a comprehensive comparison of PIM macros among DDC-PIM and other state-of-the-art studies, which can be categorized into the analog domain [11], [24], [33], [34], [35] and digital domain [14], [26].”
BackgroundImproving the Accuracy of Analog-Based In-Memory Computing Accelerators Post-Training
Lammie, C., Vasilopoulos, A., Büchel, J., Camposampiero, G., Gallo, M. L., Rasch, M. J., & Sebastian, A. (2024) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas58744.2024.10558540 · Cited by 11
Self-citationSo, H., Kim, S., & Kim, S. (2024) · Journal of Alloys and Compounds · doi:10.1016/j.jallcom.2024.175644 · Cited by 10
Dual in-memory computing of matrix-vector multiplication for accelerating neural networks
Wang, S., & Sun, Z. (2024) · Device · doi:10.1016/j.device.2024.100546 · Cited by 10
ArPCIM: An Arbitrary-Precision Analog Computing-in-Memory Accelerator With Unified INT/FP Arithmetic
Zhou, Z., Li, J., Jia, H., Yang, L., Zhou, H., Bao, H., Fu, Y., Li, Y., & Miao, X. (2024) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2024.3491825 · Cited by 12
“Conversely, ACIM relies on emerging non-volatile memory, such as resistive random-access memory (ReRAM) [2], [3], phase change memory [7], ferroelectric random-access memory [8], and magnetic random-access memory [9], offering high storage density, low cost and high energy efficiency [10], [11].”
Vu, T. T. H., Park, M. H., Phan, T. L., Park, H. J., Vũ, V. T., Kim, H. J., Aggarwal, P., Won, U. Y., Li, H., Kim, W. K., et al. (2025) · Applied Surface Science · doi:10.1016/j.apsusc.2025.162460 · Cited by 10
Metadata
- Authors
- Le Gallo, M., Khaddam-Aljameh, R., Stanisavljevic, M., Vasilopoulos, A., Kersting, B., Dazzi, M., Karunaratne, G., Brändli, M., Singh, A., Müller, S. M., Büchel, J., Timoneda, X., Joshi, V., Rasch, M. J., Egger, U., Garofalo, A., Petropoulos, A., Antonakopoulos, T., Brew, K., Choi, S., Ok, I., Philip, T., Chan, V., Silvestre, C., Ahsan, I., Saulnier, N., Narayanan, V., Francese, P. A., Eleftheriou, E., & Sebastian, A.
- Affiliations
- IBM Research - Zurich (CH)
- IBM (Germany) (DE)
- IBM (United States) (US)
- University of Patras (GR)
- IBM Research - Albany (US)
- Corresponding author
- Sebastian, Abu
- ORCID
- Le Gallo, Manuel
- Khaddam-Aljameh, Riduan
- Vasilopoulos, Athanasios
- Kersting, Benedikt
- Dazzi, Martino
- Karunaratne, Geethan
- Singh, Abhairaj
- Büchel, Julian
- Timoneda, Xavier
- Joshi, Vinay
- Rasch, Malte J.
- Garofalo, Angelo
- Petropoulos, Anastasios
- Antonakopoulos, Theodore
- Brew, Kevin
- Philip, Timothy
- Chan, Victor
- Saulnier, Nicole
- Narayanan, Vijay
- Francese, Pier Andrea
- Sebastian, Abu
- Venue
- Nature Electronics
- Published
- 2023-08-10
- Volume
- 6
- Issue
- 9
- Pages
- 680-693
- ISSN
- 2520-1131 (ISSN-L)
- OpenAlex
- W4385896568
- Semantic Scholar
- e28c05440f28c2092a251cf413f2a9d3c90fd1bb
- Cited by
- 310
- References
- 49
- Citations by year
- 2026: 78 · 2025: 130 · 2024: 79 · 2023: 23
- FWCI
- 23.00
- Type
- journal article
- Language
- en
- Open access
- green
- arxiv.org
- Licence
- Locations
- Nature Electronics (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna) (submittedVersion, other-oa)
- arXiv (Cornell University) (cc-by)
- Funders
- European Commission (HORIZON2020, 682675)
- H2020 European Research Council (966764)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Analog and Mixed-Signal Circuit Design
- Keywords
- phase-change memory, deep neural network inference, network-on-chip, ResNet, energy efficiency, resistive memory devices
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
A language model drew the claims from the paper on 2026-10-07, under version 3 of the claim definition (model deepseek-v4.1-flash, prompt extract-v3).
A second model labelled each claim on 2026-10-07 (model jev-1.13-20260917, definition revision gold-guideline-v0.2).
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
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