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A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference
Open accessAbstract
A multicore analogue in-memory computing chip that is designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory can be used for deep neural network inference. Analogue in-memory computing (AIMC) with resistive memory devices could reduce the latency and energy consumption of deep neural network inference tasks by directly performing computations within memory. However, to achieve end-to-end improvements in latency and energy consumption, AIMC must be combined with on-chip digital operations and on-chip communication. Here we report a multicore AIMC chip designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory. The fully integrated chip features 64 AIMC cores interconnected via an on-chip communication network. It also implements the digital activation functions and additional processing involved in individual convolutional layers and long short-term memory units. With this approach, we demonstrate near-software-equivalent inference accuracy with ResNet and long short-term memory networks, while implementing all the computations associated with the weight layers and the activation functions on the chip. For 8-bit input/output matrix–vector multiplications, in the four-phase (high-precision) or one-phase (low-precision) operational read mode, the chip can achieve a maximum throughput of 16.1 or 63.1 tera-operations per second at an energy efficiency of 2.48 or 9.76 tera-operations per second per watt, respectively.
Overview
AI snapshot
Written from a shortened version of the paper’s full text (it is longer than we read).
TL;DR
Hermes is a 64-core analog in-memory compute chip in 14-nm CMOS with backend-integrated phase-change memory, designed to run deep neural network inference with on-chip digital operations and communication. It demonstrates near software-equivalent accuracy on ResNet and LSTM tasks while achieving 63.1 TOPS and 9.76 TOPS W−1 for 8-bit input/output matrix-vector multiplications.
Key findings
- The chip contains 64 cores, each with a 256×256 PCM crossbar, enabling up to 4,194,304 weights on-chip; it is fabricated in 14-nm CMOS, measures 12 mm × 12 mm, and uses 418 communication links implementing a 5 Parallel Prism topology.
- On 63 of 64 cores, more than 99% of unit cells can be programmed to |G_RESET| smaller than 5 ADC counts and G_SET larger than 50 ADC counts; the outlier core has 98.4% yield. One-device-per-weight (ODP) programming achieves precision close to 3-bit weights, while two-device-per-weight (TDP) achieves between 3-bit and 4-bit weights.
- For ResNet-9 on CIFAR-10, Hermes achieves 92.81% accuracy with TDP and 92.23% with ODP, versus a software baseline of 93.67%; digital quantization adds another 0.2–0.3% drop. The chip reaches a maximal throughput of 63.1 TOPS at 9.76 TOPS W−1 for 8-bit input/output MVMs, with MVM throughput per area >15× higher than comparable multi-core resistive-memory AIMC chips.
- The paper reports near software-equivalent inference accuracy for ResNet and LSTM networks, including CIFAR-10 image recognition, Penn Treebank character prediction, and Flickr8k image caption generation, with all weight-layer computations and activation functions performed on-chip.
Methods
- The chip integrates 64 AIMC cores with backend PCM, per-row current-controlled oscillator ADCs, local digital processing units (LDPUs), global digital processing units (GDPUs), and link controllers. Each unit cell uses four PCM devices (two per polarity).
- MVM accuracy was characterized across all 64 cores using uniformly distributed 30% sparse weight matrices and 2,048 input vectors; errors were decomposed into total, linear (weight programming), and residual contributions. Two closed-loop iterative programming algorithms, ODP and TDP, were compared.
- DNN inference used hardware-aware training with noise injection on synaptic weights via the IBM Analog Hardware Acceleration Kit. Trained weights were mapped to conductances; ResNet-9, PTB LSTM, and Flickr8k LSTM networks were run with on-chip MVMs, activation functions, batch normalization, LSTM cell-state computation, aggregation, bias addition, and affine scaling. Max-pooling and embeddings were performed in software.
Limitations
- The paper states that max-pooling in ResNet-9 and character/image/word embedding in the LSTM networks are not supported by the chip and are performed in software.
- The paper states that PCM conductance drift causes linear and total MVM error to increase over time; TDP shows noticeable residual error due to sampling a wider, more nonlinear ADC range and higher leakage from non-RESET devices.
- Evident from the provided text: the excerpt is truncated before the full PTB and Flickr8k accuracy results, so those specific numbers cannot be summarized here.
Model-written summary. Check it against the paper before relying on it.
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Claims the paper makes
7 No basis given · 5 Own result · 2 Own interpretation · 1 Not checked yet
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In the paper
“while achieving the highest accuracy on the CIFAR-10 benchmark.”
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In the paper
“The yield of the remaining outlier core is 98.4%.”
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“The fully-integrated chip features 64 256x256 AIMC cores interconnected via an on-chip communication network.”
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“With TDP, a precision between 3-bit and 4-bit weights is achieved.”
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A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“When using TDP, ε linear is significantly reduced compared with ODP”
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“software baseline of 93.67%”
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In the paper
“The biggest accuracy drop from the software baseline comes from the weight error”
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In the paper
“which is less than 1% below the software baseline of 93.67%”
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In the paper
“We attribute this reduction to a higher signal-to-noise ratio achieved when using two devices instead of one20.”
What the sources say
- Not checked yetcites [20] Khwa, W.-S. et al. A 40-nm, 2M-cell, 8b-precision, hybrid SLC-MLC PCM computing-in-memory macro with 20.5–65.0TOPS/W for tiny-Al edge devices. in 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1–3 (IEEE, 2022). source
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In the paper
“showing that the weight programming error is effectively lowered when using more devices per weight.”
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- Probably not a substantial claim. 2
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“The LSTM network for PTB character prediction (1,299,312 weights and 2,066 biases)”
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“ε linear and thus also ε total increase over time as shown in Fig. 2d.”
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“It also implements the digital activation functions and processing involved in ResNet convolutional neural networks and long short-term memory (LSTM) networks.”
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“The custom ResNet-9 network (1,866,536 synaptic weights and 10 biases)”
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Probably not a substantial claim. The paper’s conclusions may not depend on it.
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“The chip can achieve a maximal throughput of 63.1 TOPS at an energy efficiency of 9.76 TOPS W−1 for 8-bit input/output matrix-vector multiplications.”
plain- Asserted: passes — The authors put it forward as true.
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Claims other papers make about this one
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“The most advanced studies in this field have reported fully integrated memristor-based compute-in-memory systems48,53–55,58,59,61,71–73, but a systematic description of essential details on the device structure or circuit architecture are generally lacking in these reports.”
From Hardware implementation of memristor-based artificial neural networks (2024) · cites this paper as [73]
Experimental — accuracy not yet measuredThe source backs part of the claim, not all of it — or backs it for a different population, condition or comparison.
In the citing paper
“For instance in a recent study54, a ResNet9 CNN was trained with a similar general HWA training approach yielding vastly improved AIMC accuracy in hardware.”
From Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (2023) · cites this paper as [54]
Experimental — accuracy not yet measuredThe source backs part of the claim, not all of it — or backs it for a different population, condition or comparison.
In the citing paper
“It has been already verified in hardware, however, that HWA training using noise injection is very effective at improving the robustness for selected (smaller) DNNs.”
From Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (2023) · cites this paper as [54]
Experimental — accuracy not yet measured
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Self-citationA Multi-Memristive Unit-Cell Array With Diagonal Interconnects for In-Memory Computing
Khaddam-Aljameh, R., Martemucci, M., Kersting, B., Gallo, M. L., Bruce, R. L., BrightSky, M. J., & Sebastian, A. (2021) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2021.3078614 · Cited by 5
Self-citationRasch, M. J., Mackin, C., Gallo, M. L., et al. (2023) · arXiv (Cornell University) · doi:10.48550/arxiv.2302.08469 · Cited by 3
Self-citation
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Cited by
Sorted by citations
Hardware implementation of memristor-based artificial neural networks
Aguirre, F., Sebastian, A., Le Gallo, M., Song, W., Wang, T., Yang, J. J., Lu, W., Chang, M.-F., Ielmini, D., Yang, Y., et al. (2024) · Nature Communications · doi:10.1038/s41467-024-45670-9 · Cited by 564
Self-citationMemristor‐Based Neuromorphic Chips
Duan, X., Cao, Z., Gao, K., Yan, W., Sun, S., Zhou, G., Wu, Z., Ren, F., & Sun, B. T. (2024) · Advanced Materials · doi:10.1002/adma.202310704 · Cited by 446
Neuromorphic computing at scale
Kudithipudi, D., Schuman, C. D., Vineyard, C. M., Pandit, T., Merkel, C. E., Kubendran, R. C., Aimone, J. B., Orchard, G., Mayr, C., Benosman, R. B., et al. (2025) · Nature · doi:10.1038/s41586-024-08253-8 · Cited by 441
“However, the full potential of these devices in large-scale systems is only beginning to be fully exploited 156 owing to several challenges, such as device non-idealities, challenges in integration with CMOS, and leakage.”
Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems
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Self-citationThe growing memristor industry
Lanza, M., Pazos, S. M., Aguirre, F. L., Sebastian, A., Gallo, M. L., Alam, S. M., Ikegawa, S., Yang, J. J., Vianello, E., Chang, M., et al. (2025) · Nature · doi:10.1038/s41586-025-08733-5 · Cited by 189
“…variability issue can be mitigated by programming multi-device cells through write–verify iterations (around 5% average weight error in two-device PCM 91 and less than 0.1% error in up to 3-device RRAM 92 ) and denoising (down to 0.2% demonstrated in RRAM with up to 200 programming iterations 93 ).”
InfluentialSelf-citation
Metadata
- Authors
- Le Gallo, M., Khaddam-Aljameh, R., Stanisavljevic, M., Vasilopoulos, A., Kersting, B., Dazzi, M., Karunaratne, G., Brändli, M., Singh, A., Müller, S. M., Büchel, J., Timoneda, X., Joshi, V., Rasch, M. J., Egger, U., Garofalo, A., Petropoulos, A., Antonakopoulos, T., Brew, K., Choi, S., Ok, I., Philip, T., Chan, V., Silvestre, C., Ahsan, I., Saulnier, N., Narayanan, V., Francese, P. A., Eleftheriou, E., & Sebastian, A.
- Affiliations
- IBM Research - Zurich (CH)
- IBM (Germany) (DE)
- IBM (United States) (US)
- University of Patras (GR)
- IBM Research - Albany (US)
- Corresponding author
- Sebastian, Abu
- ORCID
- Le Gallo, Manuel
- Khaddam-Aljameh, Riduan
- Vasilopoulos, Athanasios
- Kersting, Benedikt
- Dazzi, Martino
- Karunaratne, Geethan
- Singh, Abhairaj
- Büchel, Julian
- Timoneda, Xavier
- Joshi, Vinay
- Rasch, Malte J.
- Garofalo, Angelo
- Petropoulos, Anastasios
- Antonakopoulos, Theodore
- Brew, Kevin
- Philip, Timothy
- Chan, Victor
- Saulnier, Nicole
- Narayanan, Vijay
- Francese, Pier Andrea
- Sebastian, Abu
- Venue
- Nature Electronics
- Published
- 2023-08-10
- Volume
- 6
- Issue
- 9
- Pages
- 680-693
- ISSN
- 2520-1131 (ISSN-L)
- OpenAlex
- W4385896568
- Semantic Scholar
- e28c05440f28c2092a251cf413f2a9d3c90fd1bb
- Cited by
- 310
- References
- 49
- Citations by year
- 2026: 78 · 2025: 130 · 2024: 79 · 2023: 23
- FWCI
- 23.00
- Type
- journal article
- Language
- en
- Open access
- green
- arxiv.org
- Licence
- Locations
- Nature Electronics (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna) (submittedVersion, other-oa)
- arXiv (Cornell University) (cc-by)
- Funders
- European Commission (HORIZON2020, 682675)
- H2020 European Research Council (966764)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Analog and Mixed-Signal Circuit Design
- Keywords
- phase-change memory, deep neural network inference, network-on-chip, ResNet, energy efficiency, resistive memory devices
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
A language model drew the claims from the paper on 2026-10-07, under version 3 of the claim definition (model deepseek-v4.1-flash, prompt extract-v3).
A second model labelled each claim on 2026-10-07 (model jev-1.13-20260917, definition revision gold-guideline-v0.2).
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
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