The DOI matches its Crossref record; 50 of the 50 references it cites were found in a registry or an index; none of the 1 sources its claims cite is checked for support yet.
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference
Open accessAbstract
A multicore analogue in-memory computing chip that is designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory can be used for deep neural network inference. Analogue in-memory computing (AIMC) with resistive memory devices could reduce the latency and energy consumption of deep neural network inference tasks by directly performing computations within memory. However, to achieve end-to-end improvements in latency and energy consumption, AIMC must be combined with on-chip digital operations and on-chip communication. Here we report a multicore AIMC chip designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory. The fully integrated chip features 64 AIMC cores interconnected via an on-chip communication network. It also implements the digital activation functions and additional processing involved in individual convolutional layers and long short-term memory units. With this approach, we demonstrate near-software-equivalent inference accuracy with ResNet and long short-term memory networks, while implementing all the computations associated with the weight layers and the activation functions on the chip. For 8-bit input/output matrix–vector multiplications, in the four-phase (high-precision) or one-phase (low-precision) operational read mode, the chip can achieve a maximum throughput of 16.1 or 63.1 tera-operations per second at an energy efficiency of 2.48 or 9.76 tera-operations per second per watt, respectively.
Overview
AI snapshot
Written from a shortened version of the paper’s full text (it is longer than we read).
TL;DR
Hermes is a 64-core analog in-memory compute chip in 14-nm CMOS with backend-integrated phase-change memory, designed to run deep neural network inference with on-chip digital operations and communication. It demonstrates near software-equivalent accuracy on ResNet and LSTM tasks while achieving 63.1 TOPS and 9.76 TOPS W−1 for 8-bit input/output matrix-vector multiplications.
Key findings
- The chip contains 64 cores, each with a 256×256 PCM crossbar, enabling up to 4,194,304 weights on-chip; it is fabricated in 14-nm CMOS, measures 12 mm × 12 mm, and uses 418 communication links implementing a 5 Parallel Prism topology.
- On 63 of 64 cores, more than 99% of unit cells can be programmed to |G_RESET| smaller than 5 ADC counts and G_SET larger than 50 ADC counts; the outlier core has 98.4% yield. One-device-per-weight (ODP) programming achieves precision close to 3-bit weights, while two-device-per-weight (TDP) achieves between 3-bit and 4-bit weights.
- For ResNet-9 on CIFAR-10, Hermes achieves 92.81% accuracy with TDP and 92.23% with ODP, versus a software baseline of 93.67%; digital quantization adds another 0.2–0.3% drop. The chip reaches a maximal throughput of 63.1 TOPS at 9.76 TOPS W−1 for 8-bit input/output MVMs, with MVM throughput per area >15× higher than comparable multi-core resistive-memory AIMC chips.
- The paper reports near software-equivalent inference accuracy for ResNet and LSTM networks, including CIFAR-10 image recognition, Penn Treebank character prediction, and Flickr8k image caption generation, with all weight-layer computations and activation functions performed on-chip.
Methods
- The chip integrates 64 AIMC cores with backend PCM, per-row current-controlled oscillator ADCs, local digital processing units (LDPUs), global digital processing units (GDPUs), and link controllers. Each unit cell uses four PCM devices (two per polarity).
- MVM accuracy was characterized across all 64 cores using uniformly distributed 30% sparse weight matrices and 2,048 input vectors; errors were decomposed into total, linear (weight programming), and residual contributions. Two closed-loop iterative programming algorithms, ODP and TDP, were compared.
- DNN inference used hardware-aware training with noise injection on synaptic weights via the IBM Analog Hardware Acceleration Kit. Trained weights were mapped to conductances; ResNet-9, PTB LSTM, and Flickr8k LSTM networks were run with on-chip MVMs, activation functions, batch normalization, LSTM cell-state computation, aggregation, bias addition, and affine scaling. Max-pooling and embeddings were performed in software.
Limitations
- The paper states that max-pooling in ResNet-9 and character/image/word embedding in the LSTM networks are not supported by the chip and are performed in software.
- The paper states that PCM conductance drift causes linear and total MVM error to increase over time; TDP shows noticeable residual error due to sampling a wider, more nonlinear ADC range and higher leakage from non-RESET devices.
- Evident from the provided text: the excerpt is truncated before the full PTB and Flickr8k accuracy results, so those specific numbers cannot be summarized here.
Model-written summary. Check it against the paper before relying on it.
Integrity signals
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Claims the paper makes
7 No basis given · 5 Own result · 2 Own interpretation · 1 Not checked yet
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“while achieving the highest accuracy on the CIFAR-10 benchmark.”
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A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“The yield of the remaining outlier core is 98.4%.”
plainSingle case- Asserted: passes — The authors put it forward as true.
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- Load-bearing: unclear — It is unclear whether the paper’s conclusions depend on it.
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“The fully-integrated chip features 64 256x256 AIMC cores interconnected via an on-chip communication network.”
plain- Asserted: passes — The authors put it forward as true.
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- Load-bearing: passes — The paper’s conclusions depend on it.
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“With TDP, a precision between 3-bit and 4-bit weights is achieved.”
plaindirect- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: passes — The paper’s conclusions depend on it.
- Based: passes — The paper gives a reason why it holds.
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“When using TDP, ε linear is significantly reduced compared with ODP”
plaindirect- Asserted: passes — The authors put it forward as true.
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- Load-bearing: passes — The paper’s conclusions depend on it.
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“software baseline of 93.67%”
plain- Asserted: passes — The authors put it forward as true.
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- Load-bearing: passes — The paper’s conclusions depend on it.
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A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“The biggest accuracy drop from the software baseline comes from the weight error”
plaindirect- Asserted: passes — The authors put it forward as true.
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A conclusion the paper draws from its own results — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“which is less than 1% below the software baseline of 93.67%”
plain- Asserted: passes — The authors put it forward as true.
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In the paper
“We attribute this reduction to a higher signal-to-noise ratio achieved when using two devices instead of one20.”
What the sources say
- Not checked yetcites [20] Khwa, W.-S. et al. A 40-nm, 2M-cell, 8b-precision, hybrid SLC-MLC PCM computing-in-memory macro with 20.5–65.0TOPS/W for tiny-Al edge devices. in 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1–3 (IEEE, 2022). source
plaindirect- Asserted: passes — The authors put it forward as true.
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A conclusion the paper draws from its own results — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“showing that the weight programming error is effectively lowered when using more devices per weight.”
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- Probably not a substantial claim. 2
- It may state two separate claims as one. 3
The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“The LSTM network for PTB character prediction (1,299,312 weights and 2,066 biases)”
plain- Asserted: passes — The authors put it forward as true.
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Probably not a substantial claim. The paper’s conclusions may not depend on it.
The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“ε linear and thus also ε total increase over time as shown in Fig. 2d.”
plaindirect- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: unclear — It is unclear whether the paper’s conclusions depend on it.
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It may state two separate claims as one.
The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“It also implements the digital activation functions and processing involved in ResNet convolutional neural networks and long short-term memory (LSTM) networks.”
plain- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: passes — The paper’s conclusions depend on it.
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It may state two separate claims as one.
The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“The custom ResNet-9 network (1,866,536 synaptic weights and 10 biases)”
plain- Asserted: passes — The authors put it forward as true.
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- Load-bearing: fails — The paper’s conclusions may not depend on it.
- Based: passes — The paper gives a reason why it holds.
Probably not a substantial claim. The paper’s conclusions may not depend on it.
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“The chip can achieve a maximal throughput of 63.1 TOPS at an energy efficiency of 9.76 TOPS W−1 for 8-bit input/output matrix-vector multiplications.”
plain- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
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Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
The source backs part of the claim, not all of it — or backs it for a different population, condition or comparison.
In the citing paper
“The most advanced studies in this field have reported fully integrated memristor-based compute-in-memory systems48,53–55,58,59,61,71–73, but a systematic description of essential details on the device structure or circuit architecture are generally lacking in these reports.”
From Hardware implementation of memristor-based artificial neural networks (2024) · cites this paper as [73]
Experimental — accuracy not yet measuredThe source backs part of the claim, not all of it — or backs it for a different population, condition or comparison.
In the citing paper
“For instance in a recent study54, a ResNet9 CNN was trained with a similar general HWA training approach yielding vastly improved AIMC accuracy in hardware.”
From Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (2023) · cites this paper as [54]
Experimental — accuracy not yet measuredThe source backs part of the claim, not all of it — or backs it for a different population, condition or comparison.
In the citing paper
“It has been already verified in hardware, however, that HWA training using noise injection is very effective at improving the robustness for selected (smaller) DNNs.”
From Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (2023) · cites this paper as [54]
Experimental — accuracy not yet measured
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Background
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Efficient Hardware-aware Neural Architecture Search for Edge Computing
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Dual In-Memory Computing of Matrix-Vector MultiplicationPreprint
Wang, S., & Sun, Z. (2024) · SSRN Electronic Journal · doi:10.2139/ssrn.4821734
Xu, P., Mou, X., Gao, B., Wei, Q., Yao, P., Tang, J., Qian, H., & Wu, H. (2024) · IEEE Transactions on Circuits & Systems II Express Briefs · doi:10.1109/tcsii.2024.3442873
“Finally, Table III shows comparisons of IPIS + DIBR to the recent nvCIMs [20], [21], [22].”
Han, L., Huang, P. C., Zhou, Z., Chen, Y., Yang, H., Liu, X., & Kang, J. (2024) · Design, Automation, and Test in Europe · doi:10.23919/date58400.2024.10546661
Improving model robustness to weight noise via consistency regularization
Hou, Y., Zhang, Q., Wang, N., & Wu, H. (2024) · Machine Learning Science and Technology · doi:10.1088/2632-2153/ad734a
Analog AI as a Service: A Cloud Platform for In-Memory Computing
Maghraouir, K. E., Tran, K., Ruby, K., Godoy, B., Murray, J., Gallo, M. L., Deshane, T., Gonzalez, P., Moreda, D., Benmeziane, H., et al. (2024) · IEEE International Conference on Software Services Engineering (SSE) · doi:10.1109/sse62657.2024.00019
“An AIMC chip typically comprises multiple crossbar arrays of memory devices that communicate with each other [9].”
BackgroundSelf-citationUtilizing MRAMs With Low Resistance and Limited Dynamic Range for Efficient MAC Accelerator
Sateesh, Chakarwar, K., & Sahay, S. (2024) · IEEE Open Journal of Nanotechnology · doi:10.1109/ojnano.2024.3501293
“However, these hardware accelerators exploit MRAM cells with single-level capability (SLC) [11].”
Ultralow Power Cold-Fuse Memory Based on Metal-Oxide-CNT Structure
Chen, W., Li, X., Ma, X., Zhu, L., Hu, Y., Peng, L., & Qiu, C. (2025) · Nano Letters · doi:10.1021/acs.nanolett.4c06103
GLoRia: An Energy-Efficient GPU-RRAM System Stack for Large Neural Networks
de Moura, R. F., Jordan, M. G., & Carro, L. (2025) · Lecture notes in computer science · doi:10.1007/978-3-031-78377-7_15
HyperMR: Efficient Hypergraph-enhanced Matrix Storage on Compute-in-Memory Architecture
Wu, Y., Chen, K., Chen, G., Jiang, D., Li, H., & Shou, L. (2025) · Proceedings of the ACM on Management of Data · doi:10.1145/3709695
The mechanism of electrical conduction in glassy semiconductors
Kurnosov, A. A., & Lubchenko, V. (2025) · Proceedings of the National Academy of Sciences · doi:10.1073/pnas.2414650122
Jiao, Z., Chen, X., Hong, T., Dai, W., Tu, C., Li, S., Chen, H., & Song, Z. (2024) · IEEE High Performance Extreme Computing Conference · doi:10.1109/hpec62836.2024.10938478
Tomato Leaf Disease Detection and Classification using GAN and ResNet-9
Kaur, P., Kaur, K., Kaur, P., Kaur, V., & Gupta, M. (2025) · Recent Advances in Computer Science and Communications · doi:10.2174/0126662558365090250318014139
Analog In-Memory Computing for the Synthetic Aperture Radar Polar Format Algorithm
Richardson, D. K., Xiao, T. P., West, R. D., Bennett, C. H., & Agarwal, S. (2025) · IEEE Transactions on Radar Systems · doi:10.1109/trs.2025.3570977
“However, [37] provides area and throughput metrics for a number of chips performing neural network tasks.”
Live Demonstration: Automated DNN Deployment on the IBM HERMES Project Chip
Lammie, C., Büchel, J., Vasilopoulos, A., Camposampiero, G., Noussi, L., Simon, W., Gallo, M. L., & Sebastian, A. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11043202
Self-citationA framework for analog-digital mixed-precision neural network training and inference
Vasilopoulos, A., Boulharts, E., Lammie, C., Büchel, J., Benmeziane, H., Gallo, M. L., & Sebastian, A. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11043537
“Additionally, we introduce a new tile, called QuantizedTorchInferenceTile , whose final output is again quantized down to a configurable size, independent of the precision of the analog-to-digital converters, as it is the case in modern AIMC designs [5].”
Self-citationA deep learning model for ocean surface latent heat flux based on transformer and data assimilation
Liu, Y., Li, H., & Wang, J. (2025) · Acta Oceanologica Sinica · doi:10.1007/s13131-024-2392-x
Yu, R., Zou, C., Li, J., Gao, B., Tang, J., Qian, H., & Wu, H. (2025) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2025.3600366
“This design confers a significant energy advantage over traditional CMOS-based computing hardware [12], [13], [14], [15].”
CIMFlow: Modelling Dataflow in Cross-Layer Compute-in-Memory Deep Learning Accelerators
Cubero-Cascante, J., Schneider, L. T. R., Pelke, R., Vaidyanathan, A. M., Leupers, R., & Joseph, J. M. (2025) · ACM Transactions on Embedded Computing Systems · doi:10.1145/3760780
Speeding up fermionic lattice calculations with photonic accelerated inverters
Attanasio, F., Bauer, M., Dijkstra, J., Lee, T. D., Pawlowski, J. M., Pernice, W. H. P., & Brückerhoff-Plückelmann, F. (2025) · Computer Physics Communications · doi:10.1016/j.cpc.2025.109825
ThRIve: Thermally Robust CNN Inference via Low-Rank Adaptation in Heterogeneous PIM Architectures
Sharma, V., Dhingra, P., Doppa, J. R., & Pande, P. P. (2025) · ACM Transactions on Design Automation of Electronic Systems · doi:10.1145/3774328
Takaghaj, S. M. (2025) · International Joint Conference on Neural Networks (IJCNN) · doi:10.1109/ijcnn64981.2025.11229386
Predicting sampling advantage of stochastic Ising machines for quantum simulations
Berns, R. J. L. F., Rodrigues, D. R., Finocchio, G., & Mentink, J. H. (2026) · Physical Review Applied · doi:10.1103/xl6n-dlq6
“Furthermore, there are four sIM implementations: CPU-based implementation, FPGA running at 70 MHz [33], conservative projection based on [34], and optimistic projection based on [5]. of sIM and MH can differ by orders of magnitude.”
InfluentialSAGE: Saliency-Aware Grouping for Efficient Mapping of LLMs on Analog Compute-in-Memory
Hou, Y. T., Liu, Z., Gagnon, G., Tsai, H.-Y. S., Maghraoui, K. E., Burr, G. W., & Liu, L. (2025) · doi:10.1109/iccad66269.2025.11240907
“To enable scalable and energy-efficient LLM inference, our system adopts a heterogeneous multi-chip architecture inspired by prior work on large-scale CIM integration [5], [9], [10], [17], [21], [38], [40].”
Analyzing Embedded Non-Volatile Memory and Technology Optimizations for In-Memory Computing
Deaville, P., Zhang, B., & Verma, N. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3632212
A Dimensional Order Search Based Mapping Algorithm for Deploying DNNs Onto Many-Core Neuromorphic IC
Wang, S., Lu, R., Xiao, B., Wang, Z., Guo, Y., Sun, X., & Yu, W. (2025) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2025.3640508
“D mesh configuration due to its demonstrated advantages in high throughput and scalability, as evidenced by numerous studies [5], [6], [7], [8], [9], [10], [17], [21], [22].”
Neuromorphic Computing With Emerging Memories
Zhao, R., & Yang, J. J. (2025) · Computer · doi:10.1109/mc.2025.3615214
Sakemi, Y., Awano, H., & Morie, T. (2025) · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · doi:10.1587/transfun.2025gci0001
All-Optically Switchable Platform Based on Phase-Change Material for Light-Emitting Device
Kushchenko, O. M., Bodiago, E., Litvinov, D. A., Lazarenko, P., Kozyukhin, S. A., Рыбин, М. В., Gets, D. S., & Sinelnik, A. D. (2025) · ACS Applied Materials & Interfaces · doi:10.1021/acsami.5c18195
Integrated Photonics for Neuromorphic Computing
Meyer, L., Xu, R., & Pernice, W. H. P. (2026) · Machine intelligence for materials science · doi:10.1007/978-3-032-04129-6_17
Fiber-integrated phase-change microsphere system for all-optical modulation and computing
Sun, J., Wang, J., Liu, Y., Bo, F., Zhang, Y., Li, H., Liu, L., & Liu, Z. (2026) · Smart Photonic and Optoelectronic Integrated Circuits · doi:10.1117/12.3079648
One-Time Programmable Read-Write Mechanism Based on Analog-Digital Hybrid Design
Huang, Q., Zhang, X. H., Luo, Y., Ge, G., Wen, J., & Guan, K. (2025) · International Conference on Electronic Information Engineering and Computer Technology (EIECT) · doi:10.1109/eiect68017.2025.11331831
Associative clustering with analog content-addressable memory
Ameli, S., Yu, J., & Strachan, J. P. (2025) · International Symposium on Memory Systems (MEMSYS) · doi:10.1145/3767110.3767132
Yan, S., Qian, Z., Fu, X., Zeyu, G. U. O., Li, Z., Wang, J., Wang, L., Wu, Z., Xu, X., Dou, C., et al. (2026) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2026.3660209
“Phase-change memory (PCM), an emerging nonvolatile memory and on-chip cache candidate, su ff ers from high write energy and poor thermal stability [33], [34].”
NeoHebbian synapses to accelerate online training of neuromorphic hardware
Pande, S. R., Bezugam, S. S., Bhattacharya, T., Wlaźlak, E., Chakravorty, A., Chakrabarti, B., & Strukov, D. B. (2026) · Scientific Reports · doi:10.1038/s41598-026-35641-z
“Several studies have reported chip-level demonstrations of neural network accelerators using various memristive devices 14–17 .”
Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators
Krestinskaya, O., Fouda, M. E., Eltawil, A. M., & Salama, K. N. (2026) · IEEE Access · doi:10.1109/access.2026.3671360 · Cited by 2
“This leads to significant gains in energy efficiency, performance, and throughput [9]–[12].”
Wang, Y., Zhao, P., & Sun, J. (2026) · IEEE Transactions on NanoBioscience · doi:10.1109/tnb.2026.3673367
“The neural network realizes the functions of learning and memory by simulating the connection and information transmission of neurons in the brain [1], [2], [3].”
Correcting processing-in-memory multiply-accumulate arithmetic errors with LDPC
Shi, D., Fu, Y., Zhu, Y., Fan, A., Tao, Y., Yan, B. Y., & Yang, Y. (2026) · npj Unconventional Computing · doi:10.1038/s44335-026-00061-9
Quantum-enhanced reconfigurable in-memory stochastic computing
Yang, H.-Z., Dou, J.-P., Lu, F., Shang, X.-W., Zhang, C.-N., Zhou, H., Tang, H. L., & Jin, X. (2026) · Light Science & Applications · doi:10.1038/s41377-025-02181-6
“…various memory mechanisms and materials, the implementations of in-memory computing have been realized in different systems ranging from electronic 22 – 27 to photonic platforms 5,28 – 32 , and in-memory computing has been commonly recognized as a promising solution for ef fi ciently processing…”
Beyond CMOS: Neuromorphic and Quantum Inspired VLSI for the Next Era of Intelligent Computing
Akram Ahamed, S., S, T. A., Vaishnavi, H., Neveythithaa, S., Yuvaraj, G., & S, A. F. A. (2026) · International Conference on Signal Processing and Electronics Design (ICSPED) · doi:10.1109/icsped65817.2026.11448357
Benmeziane, H., Lammie, C., Boybat, I., Rasch, M. J., Gallo, M. L., Vasilopoulos, A., Tsai, H.-Y. S., Burr, G. W., Narayanan, V., Maghraoui, K. E., et al. (2026) · Nature Communications · doi:10.1038/s41467-026-71071-1 · Cited by 1
Self-citationConvolutional and dynamical spintronic neural networks
Plouet, E. (2024) · theses.fr (ABES) · doi:10.70675/2bb4a111z543cz414fz820bz399226e583c6
Exploring learning techniques for edge AI taking advantage of non-volatile memories
Martemucci, M. (2024) · theses.fr (ABES) · doi:10.70675/ec79fa4cz56b6z4c04z86b9zd771c8285800
GRAS: General-Purpose and Reconfigurable Analog Solver for Matrix Computing
Pan, L., Wang, S., Zuo, P., & Sun, Z. (2026) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2026.3682645
“In recent years, in-memory analog matrix computing (AMC) with nonvolatile resistive memory, for its high speed and low power consumption, has been extensively applied to accelerate matrix computations [6], [7], [8], [9], [10], [11].”
Low-loss phase-change material-based programmable mode converter for photonic computing
Shen, X., Chu, R., Xu, D., Gao, Y., Zhou, W., & Zhang, W. (2026) · NPG Asia Materials · doi:10.1038/s41427-026-00645-8
“Using the doped Ge 2 Sb 2 Te 5 (GST) phase-change alloy, a prototype neuromorphic computing chip was shown to be capable of resolving many demanding arti fi cial intelligence (AI) tasks at high computing and energy ef fi ciencies 18 – 20 .”
SALMON: Self-Adaptive Learning Model on Neuromorphic Hardware
Cho, Y. W., Lee, S., & Kim, S. (2026) · IEEE Transactions on Neural Networks and Learning Systems · doi:10.1109/tnnls.2026.3687785
“Consequently, AIMC systems are expected to o ff er significantly faster performance and greater energy e ffi ciency compared to digital alternatives, successfully accelerating on-chip inference with pretrained models [7], [8], [9].”
Synaptic Behaviors in a Commercial Bulk Silicon MOSFET at Cryogenic Temperature
Guo, H., Zhang, Y., Chen, Y., Sheng, H., Fang, C., Xu, J. Q., Luo, C., & Guo, G. (2026) · IEEE Electron Device Letters · doi:10.1109/led.2026.3692206
“To this end, various memory-based devices have been proposed for the hardware realization of neuromorphic computing, including resistive random-access memory (RRAM) [4], [5], [6], [7], phase-change memory (PCM) [8], [9], [10], and ferroelectric field-e ff ect transistors (FeFETs) [11], [12].”
Analog Error-Correcting Codes for Dependable In-Memory Computing of Neural Networks
Jiang, A. A. (2026) · Springer eBooks · doi:10.1007/978-3-032-17948-7_7
Analog In-Memory Computing for Large Language Model Inference: Opportunities and Challenges
Vasilopoulos, A., Benmeziane, H., Büchel, J., Simon, W., Singh, A., Boybat, I., Luquin, J., Narayanan, P., Tsai, H.-Y. S., Burr, G. W., et al. (2026) · IEEE International Memory Workshop (IMW) · doi:10.1109/imw68301.2026.11532624
Self-citationKobayashi, T., Taniguchi, Y., Ikegaya, H., Tamatsu, T., Yamaguchi, M., Yanagisawa, K., Uji, Y., Yabe, T., Yoshida, S., Kawashima, Y., et al. (2026) · IEEE International Memory Workshop (IMW) · doi:10.1109/imw68301.2026.11532835
Vertical 3D Phase-Change Memory with Metallic Liner for Enhanced Resistance Drift Suppression
Choi, Y., Choi, W., Choi, J., Han, D., Kang, D., & Kim, S. (2026) · Electronic Materials Letters · doi:10.1007/s13391-026-00655-2
On the Viability of End-to-End Neural Networks in the Analog Domain
Ige, A., Ayyappan, P. R., & Hasler, J. (2026) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2026.3703087
“Mixed-signal CIM involves performing VMM in the analog domain [4], [5], [6], [8], which o ff ers greater e ffi ciency by eliminating the fundamental digital multiply and accumulate computation overhead compared to fully digital CIM approaches [9].”
Advances in Analog Architectures and Randomized Algorithms: Computational and Energy Efficiencies
Kalantzis, V., Squillante, M. S., Ubaru, S., Gokmen, T., Wu, C. W., Gupta, A., Avron, H., Nowicki, T., Rasch, M. J., Onen, M., et al. (2026) · ACM Computing Surveys · doi:10.1145/3820882
Self-citationVCMA-MRAM-Based In Situ, In-Memory Computing Architecture for Subtractors and Dividers
Tang, Q., Duan, W., Zhu, Z., Wan, M., You, L., & Song, M. (2026) · IEEE Transactions on Magnetics · doi:10.1109/tmag.2026.3704383
“Currently, non-volatile memory technologies such as magnetoresistive random access memory (MRAM) [15], [16], [17], resistive random access memory (ReRAM) [18], [19], and phase-change memory (PCM) [20], [21] are emerging as e ff ective approaches for realizing high-performance IMC.”
Area-Efficient In-Memory Computing for Mixture-of-Experts via Multiplexing and Caching
Gao, H., & Yang, X. (2026) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas66217.2026.11562485
A Data-Driven Framework for Modeling Non-Idealities in Analog In-Memory Computing Hardware
Vasilopoulos, A., Kersting, B., Büchel, J., Sebastian, A., & Gallo, M. L. (2026) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2026.3705427
“As such, the analysis below is performed separately for the one-device programming (ODP) [34] and two-device programming (TDP) [22] schemes supported by the IBM HERMES Project Chip [7].”
InfluentialSelf-citationDebets, R., Galetta, M., Negrini, T., Verest, J. F. M., Lahkar, S., Falcone, D. F., Karg, S., Bragaglia, V., & Todri‐Sanial, A. (2026) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2026.3705420
“In response, several alternative computing paradigms have been explored, including adiabatic computing [2], neuromorphic spiking-neural-network systems [3], in-memory computing using resistive memory arrays [4], [5], [6], and physical / analogue computing fabrics based on dynamical systems.”
Curvilinear mask technology for integrated circuit lithography
Chen, Z., Su, Y., Su, X., Wang, Y., ren, P., Jiang, Y., Chen, T., Meng, F., & Wei, Y. (2026) · Light Advanced Manufacturing · doi:10.37188/lam.2026.106
Analog neural network–based wireless receiver
He, C., Huang, Y., Korkmaz, A., Rad, A. J., Xia, Q., & Katehi, L. (2026) · Science Advances · doi:10.1126/sciadv.aeg7153
Tian, Y., Sheheryar, T., Wang, S., & Lv, B. (2026) · Measurement · doi:10.1016/j.measurement.2026.122604
Thomas, J., Radhakrishnan, A., Tripathi, J. N., & James, A. P. (2026) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2026.3720989
“The recent analog in-memory computing architectures [14], [15] use hardware-aware training and redundancy to manage conductance variations.”
Ricci, S., Mannocci, P., Porzani, M., Bridarolli, D., Carletti, F., Farronato, M., & Ielmini, D. (2026) · Advanced Electronic Materials · doi:10.1002/aelm.202600012
“Furthermore, to enable the solution of larger-scale problems, modular architectures comprising multiple crossbars with shared programming peripherals will be required [ 44–46 ], with arrays operating in parallel to preserve the latency advantage of IMC over classical computers.”
CIM-FLEX: An Integer-Only Flexible Periphery for Distributed Compute-In-Memory Architectures
Şanlı, İ., Rossi, M., Ferro, E., Jha, A., Burg, A. P., Singh, S. P., Boesch, T., & Boybat, I. (2026) · International Symposium on Low Power Electronics and Design (ISLPED) · doi:10.1145/3816440.3818582
Wafer-scale SOT-MRAM for analog crossbar array applications
Liu, S., Rogers, V., Hu, C., Song, M.-Y., Bao, X., & Incorvia, J. A. C. (2026) · Science Advances · doi:10.1126/sciadv.aee6952
A Stateless Reusable Crossbar Accelerator for Neural Network Inference
Papachristou, C., & Aloufi, J. (2026) · IEEE National Aerospace and Electronics Conference (NAECON) · doi:10.1109/naecon70028.2026.11675023
“More recently, HERMES [22] and NeuR-RAM [23] scale this pattern to 64 PCM and 48 RRAM cores respectively, holding network weights in non-volatile memory.”
Sle, Y., Park, J., Vincent, P., Lee, W., Jeon, J., & Cho, H. S. (2026) · Engineering Applications of Artificial Intelligence · doi:10.1016/j.engappai.2026.116185
Metadata
- Authors
- Le Gallo, M., Khaddam-Aljameh, R., Stanisavljevic, M., Vasilopoulos, A., Kersting, B., Dazzi, M., Karunaratne, G., Brändli, M., Singh, A., Müller, S. M., Büchel, J., Timoneda, X., Joshi, V., Rasch, M. J., Egger, U., Garofalo, A., Petropoulos, A., Antonakopoulos, T., Brew, K., Choi, S., Ok, I., Philip, T., Chan, V., Silvestre, C., Ahsan, I., Saulnier, N., Narayanan, V., Francese, P. A., Eleftheriou, E., & Sebastian, A.
- Affiliations
- IBM Research - Zurich (CH)
- IBM (Germany) (DE)
- IBM (United States) (US)
- University of Patras (GR)
- IBM Research - Albany (US)
- Corresponding author
- Sebastian, Abu
- ORCID
- Le Gallo, Manuel
- Khaddam-Aljameh, Riduan
- Vasilopoulos, Athanasios
- Kersting, Benedikt
- Dazzi, Martino
- Karunaratne, Geethan
- Singh, Abhairaj
- Büchel, Julian
- Timoneda, Xavier
- Joshi, Vinay
- Rasch, Malte J.
- Garofalo, Angelo
- Petropoulos, Anastasios
- Antonakopoulos, Theodore
- Brew, Kevin
- Philip, Timothy
- Chan, Victor
- Saulnier, Nicole
- Narayanan, Vijay
- Francese, Pier Andrea
- Sebastian, Abu
- Venue
- Nature Electronics
- Published
- 2023-08-10
- Volume
- 6
- Issue
- 9
- Pages
- 680-693
- ISSN
- 2520-1131 (ISSN-L)
- OpenAlex
- W4385896568
- Semantic Scholar
- e28c05440f28c2092a251cf413f2a9d3c90fd1bb
- Cited by
- 310
- References
- 49
- Citations by year
- 2026: 78 · 2025: 130 · 2024: 79 · 2023: 23
- FWCI
- 23.00
- Type
- journal article
- Language
- en
- Open access
- green
- arxiv.org
- Licence
- Locations
- Nature Electronics (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna) (submittedVersion, other-oa)
- arXiv (Cornell University) (cc-by)
- Funders
- European Commission (HORIZON2020, 682675)
- H2020 European Research Council (966764)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Analog and Mixed-Signal Circuit Design
- Keywords
- phase-change memory, deep neural network inference, network-on-chip, ResNet, energy efficiency, resistive memory devices
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