The DOI matches its Crossref record; 50 of the 50 references it cites were found in a registry or an index; none of the 1 sources its claims cite is checked for support yet.
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference
Open accessAbstract
A multicore analogue in-memory computing chip that is designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory can be used for deep neural network inference. Analogue in-memory computing (AIMC) with resistive memory devices could reduce the latency and energy consumption of deep neural network inference tasks by directly performing computations within memory. However, to achieve end-to-end improvements in latency and energy consumption, AIMC must be combined with on-chip digital operations and on-chip communication. Here we report a multicore AIMC chip designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory. The fully integrated chip features 64 AIMC cores interconnected via an on-chip communication network. It also implements the digital activation functions and additional processing involved in individual convolutional layers and long short-term memory units. With this approach, we demonstrate near-software-equivalent inference accuracy with ResNet and long short-term memory networks, while implementing all the computations associated with the weight layers and the activation functions on the chip. For 8-bit input/output matrix–vector multiplications, in the four-phase (high-precision) or one-phase (low-precision) operational read mode, the chip can achieve a maximum throughput of 16.1 or 63.1 tera-operations per second at an energy efficiency of 2.48 or 9.76 tera-operations per second per watt, respectively.
Overview
AI snapshot
Written from a shortened version of the paper’s full text (it is longer than we read).
TL;DR
Hermes is a 64-core analog in-memory compute chip in 14-nm CMOS with backend-integrated phase-change memory, designed to run deep neural network inference with on-chip digital operations and communication. It demonstrates near software-equivalent accuracy on ResNet and LSTM tasks while achieving 63.1 TOPS and 9.76 TOPS W−1 for 8-bit input/output matrix-vector multiplications.
Key findings
- The chip contains 64 cores, each with a 256×256 PCM crossbar, enabling up to 4,194,304 weights on-chip; it is fabricated in 14-nm CMOS, measures 12 mm × 12 mm, and uses 418 communication links implementing a 5 Parallel Prism topology.
- On 63 of 64 cores, more than 99% of unit cells can be programmed to |G_RESET| smaller than 5 ADC counts and G_SET larger than 50 ADC counts; the outlier core has 98.4% yield. One-device-per-weight (ODP) programming achieves precision close to 3-bit weights, while two-device-per-weight (TDP) achieves between 3-bit and 4-bit weights.
- For ResNet-9 on CIFAR-10, Hermes achieves 92.81% accuracy with TDP and 92.23% with ODP, versus a software baseline of 93.67%; digital quantization adds another 0.2–0.3% drop. The chip reaches a maximal throughput of 63.1 TOPS at 9.76 TOPS W−1 for 8-bit input/output MVMs, with MVM throughput per area >15× higher than comparable multi-core resistive-memory AIMC chips.
- The paper reports near software-equivalent inference accuracy for ResNet and LSTM networks, including CIFAR-10 image recognition, Penn Treebank character prediction, and Flickr8k image caption generation, with all weight-layer computations and activation functions performed on-chip.
Methods
- The chip integrates 64 AIMC cores with backend PCM, per-row current-controlled oscillator ADCs, local digital processing units (LDPUs), global digital processing units (GDPUs), and link controllers. Each unit cell uses four PCM devices (two per polarity).
- MVM accuracy was characterized across all 64 cores using uniformly distributed 30% sparse weight matrices and 2,048 input vectors; errors were decomposed into total, linear (weight programming), and residual contributions. Two closed-loop iterative programming algorithms, ODP and TDP, were compared.
- DNN inference used hardware-aware training with noise injection on synaptic weights via the IBM Analog Hardware Acceleration Kit. Trained weights were mapped to conductances; ResNet-9, PTB LSTM, and Flickr8k LSTM networks were run with on-chip MVMs, activation functions, batch normalization, LSTM cell-state computation, aggregation, bias addition, and affine scaling. Max-pooling and embeddings were performed in software.
Limitations
- The paper states that max-pooling in ResNet-9 and character/image/word embedding in the LSTM networks are not supported by the chip and are performed in software.
- The paper states that PCM conductance drift causes linear and total MVM error to increase over time; TDP shows noticeable residual error due to sampling a wider, more nonlinear ADC range and higher leakage from non-RESET devices.
- Evident from the provided text: the excerpt is truncated before the full PTB and Flickr8k accuracy results, so those specific numbers cannot be summarized here.
Model-written summary. Check it against the paper before relying on it.
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Claims the paper makes
7 No basis given · 5 Own result · 2 Own interpretation · 1 Not checked yet
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“while achieving the highest accuracy on the CIFAR-10 benchmark.”
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A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“The yield of the remaining outlier core is 98.4%.”
plainSingle case- Asserted: passes — The authors put it forward as true.
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- Load-bearing: unclear — It is unclear whether the paper’s conclusions depend on it.
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“The fully-integrated chip features 64 256x256 AIMC cores interconnected via an on-chip communication network.”
plain- Asserted: passes — The authors put it forward as true.
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“With TDP, a precision between 3-bit and 4-bit weights is achieved.”
plaindirect- Asserted: passes — The authors put it forward as true.
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- Load-bearing: passes — The paper’s conclusions depend on it.
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A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“When using TDP, ε linear is significantly reduced compared with ODP”
plaindirect- Asserted: passes — The authors put it forward as true.
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“software baseline of 93.67%”
plain- Asserted: passes — The authors put it forward as true.
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A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“The biggest accuracy drop from the software baseline comes from the weight error”
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In the paper
“which is less than 1% below the software baseline of 93.67%”
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In the paper
“We attribute this reduction to a higher signal-to-noise ratio achieved when using two devices instead of one20.”
What the sources say
- Not checked yetcites [20] Khwa, W.-S. et al. A 40-nm, 2M-cell, 8b-precision, hybrid SLC-MLC PCM computing-in-memory macro with 20.5–65.0TOPS/W for tiny-Al edge devices. in 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1–3 (IEEE, 2022). source
plaindirect- Asserted: passes — The authors put it forward as true.
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A conclusion the paper draws from its own results — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“showing that the weight programming error is effectively lowered when using more devices per weight.”
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- Probably not a substantial claim. 2
- It may state two separate claims as one. 3
The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“The LSTM network for PTB character prediction (1,299,312 weights and 2,066 biases)”
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Probably not a substantial claim. The paper’s conclusions may not depend on it.
The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“ε linear and thus also ε total increase over time as shown in Fig. 2d.”
plaindirect- Asserted: passes — The authors put it forward as true.
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“It also implements the digital activation functions and processing involved in ResNet convolutional neural networks and long short-term memory (LSTM) networks.”
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The paper states this without a source or data behind it here, so there is nothing to check it against. The quote shows it is in the paper.
In the paper
“The custom ResNet-9 network (1,866,536 synaptic weights and 10 biases)”
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Probably not a substantial claim. The paper’s conclusions may not depend on it.
A result the paper reports from its own data — it cites no other source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“The chip can achieve a maximal throughput of 63.1 TOPS at an energy efficiency of 9.76 TOPS W−1 for 8-bit input/output matrix-vector multiplications.”
plain- Asserted: passes — The authors put it forward as true.
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Claims other papers make about this one
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The source backs part of the claim, not all of it — or backs it for a different population, condition or comparison.
In the citing paper
“The most advanced studies in this field have reported fully integrated memristor-based compute-in-memory systems48,53–55,58,59,61,71–73, but a systematic description of essential details on the device structure or circuit architecture are generally lacking in these reports.”
From Hardware implementation of memristor-based artificial neural networks (2024) · cites this paper as [73]
Experimental — accuracy not yet measuredThe source backs part of the claim, not all of it — or backs it for a different population, condition or comparison.
In the citing paper
“For instance in a recent study54, a ResNet9 CNN was trained with a similar general HWA training approach yielding vastly improved AIMC accuracy in hardware.”
From Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (2023) · cites this paper as [54]
Experimental — accuracy not yet measuredThe source backs part of the claim, not all of it — or backs it for a different population, condition or comparison.
In the citing paper
“It has been already verified in hardware, however, that HWA training using noise injection is very effective at improving the robustness for selected (smaller) DNNs.”
From Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (2023) · cites this paper as [54]
Experimental — accuracy not yet measured
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Background
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Self-citationCompute-in-memory implementation of state space models for event sequence processing
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Diaz-Pier, S., & Carloni, P. (2024) · Current Opinion in Structural Biology · doi:10.1016/j.sbi.2024.102817 · Cited by 6
Analog Error-Correcting Codes: Designs and Analysis
Jiang, A. A. (2024) · IEEE Transactions on Information Theory · doi:10.1109/tit.2024.3454059 · Cited by 6
“(Note that when vector-matrix multiplications – an important application of Analog ECCs – are implemented in nanoscale analog circuits, the numbers in the matrix are stored in crossbar arrays of NVM cells [3], [4], [6], [10], [12].)”
BackgroundInfluentialZhu, Y., Lu, X. C., Hua, X., Liu, K., Liu, Y., Luo, M., Liu, J., Dang, Z., Liu, Y., Liu, M., et al. (2024) · Photonics Research · doi:10.1364/prj.536939 · Cited by 7
Liu, S., Wei, S.-T., Yao, P., Wu, D. M., Lu, J., Pan, S., Tang, J., Gao, B., Qian, H., & Wu, H. (2025) · Journal of Semiconductors · doi:10.1088/1674-4926/24100017 · Cited by 5
Memristive In‐Memory Object Detection with 128 Mb C‐Doped Ge 2 Sb 2 Te 5 PCM Chip
Xie, C., Li, Y., Yan, L., Song, S., Chen, H., Qi, R., Li, X., Zhu, Y., Yu, L., Yan, B., et al. (2025) · Advanced Science · doi:10.1002/advs.202505678 · Cited by 5
Ultrahigh-precision analog computing using memory-switching geometric ratio of transistors
Yangdong, X.-J., Wang, C., Zhao, Y., Wang, Z.-C., Yang, Z., Liu, Z., Yu, W., Zeng, Z., Wang, S., Wei, W., et al. (2025) · Science Advances · doi:10.1126/sciadv.ady4798 · Cited by 5
“S7), similar to that of the AIMC hardware reported in ( 33 , 42 , 45 ).”
Fayza, F., Demirkiran, C., Rao, S. S. P., Bunandar, D., Gupta, U., & Joshi, A. (2025) · Communications Physics · doi:10.1038/s42005-025-02300-0 · Cited by 6
“Notable examples include 43 – 47 , and many more that leverage different types of Non-Volatile Memory (NVM) cells such as RRAM (Resistive Random-Access Memory), FeFET (Ferroelectric Field-EffectTransistor),andPCM(Phase-ChangeMemory)forbothdatastorage and in-memory computation.”
Neuromorphic olfactory perception chips: towards universal odour recognition and cognition
Zhao, Y., Wang, J., Zhang, S., & Liang, W. (2025) · Nature Reviews Electrical Engineering · doi:10.1038/s44287-025-00214-1 · Cited by 7
Deep neural network inference on an integrated, reconfigurable photonic tensor processor
Meyer, L., Dijkstra, J., Tebeck, S., McRae, L., Bahr, N., Steinmeyer, D., Koptyaev, S. N., Bernasconi, J., Pavlov, N. G., Karpov, M., et al. (2026) · Nature Communications · doi:10.1038/s41467-026-71599-2 · Cited by 5
Demonstration of 4-quadrant analog in-memory matrix multiplication in a single modulation
Gallo, M. L., Hrynkevych, O., Kersting, B., Karunaratne, G., Vasilopoulos, A., Khaddam-Aljameh, R., Sarwat, S. G., & Sebastian, A. (2024) · npj Unconventional Computing · doi:10.1038/s44335-024-00010-4 · Cited by 5
“Note that the chip alsoallowstheuseofonlyasingledeviceperweightpolarity,whichachieves highermemorydensityattheexpenseoflowerMVMaccuracy 4 .”
BackgroundMethodInfluentialSelf-citationRACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Acceleration
Zhao, L., Natarajan, A., Buonanno, L., Gajjar, A., Roth, R. M., Serebryakov, S., Moon, J., Eldash, O., Ignowski, J., & Pedretti, G. (2025) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd65941.2025.00021 · Cited by 6
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“While crossbar arrays with symmetric signal pathways enable in-situ BP, they suffer from inflexible parallelism adjustment and precision degradation, resulting from the tight coupling between precision and input parallelism [6], [7], [8].”
Wen, 周. Z., Wanting, 马. M., Yaran, 靳. J., Xingda, 火. H., Yuan, 王. W., & Wei, 张. Z. (2025) · Laser & Optoelectronics Progress · doi:10.3788/lop250910 · Cited by 4
High-Precision Close-to-Analog Programming of PCM Cells as Devices for AiMC Edge-AI
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“The main results of this work are compared with the State-of-the-Art PCM-based AiMC systems in Table I The results achieved through the presented analog programming method reach a higher range of stored weights ˆ z MAX i,j”
In-memory analog computing for non-negative matrix factorization
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OML-PCM: optical multi-level phase change memory architecture for embedded computing systems
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“The IBM research community introduced an energy-efficient analog AI mixed signal chip for different Deep Neural Network inference tasks [158].”
MethodNORA: Noise-Optimized Rescaling of LLMs on Analog Compute-in-Memory Accelerators
Hou, Y. T., Tsai, H.-Y. S., Maghraoui, K. E., Gokmen, T., Burr, G. W., & Liu, L. (2025) · Design, Automation, and Test in Europe · doi:10.23919/date64628.2025.10993217 · Cited by 4
Kernel approximation using analogue in-memory computing
Büchel, J., Camposampiero, G., Vasilopoulos, A., Lammie, C., Gallo, M. L., Rahimi, A., & Sebastian, A. (2024) · Nature Machine Intelligence · doi:10.1038/s42256-024-00943-2 · Cited by 4
Self-citationEnergy-Efficient Brain Floating Point Convolutional Neural Network Using Memristors
Tong, S.-Q., Bao, H., Li, J.-C., Yang, L., Zhou, H.-J., Li, Y., & Miao, X.-S. (2024) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2024.3379953 · Cited by 3
“Table II presents a performance comparison among state-of-the-art AI processors, including SRAM and memristors for FP computing, as well as PCM for fixed-point computing [43], [44], [45], [46], [47], [48].”
BackgroundLightML: A Photonic Accelerator for Efficient General Purpose Machine Learning
Liu, L., Kari, S. R., Xin, X., Youngblood, N., Zhang, Y., & Yang, J. (2025) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1145/3695053.3731053 · Cited by 3
Memristors for Bayesian in-memory computing
Dalgaty, T., Vianello, E., & Querlioz, D. (2025) · Nature Materials · doi:10.1038/s41563-025-02409-1 · Cited by 3
In-Memory-Computing for Machine Cognition at the Edge
Andreou, A. G., Tomlinson, M. A., Niu, R., Malik, A., Debrah, K. B., Psaltakis, G., Mendat, D. R., Pouliquen, P. O., Molin, J. L., Bottone, S., et al. (2026) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2026.3669179 · Cited by 3
“This is a well-established procedure known as Hardware Aware Training (HAT) that has been shown to achieve iso-accuracy, or near iso-accuracy with as few as 3 bits bit-depth [38], and there is a plethora of methods, and a number of programming tools, from which a practitioner can choose [38].”
InfluentialAccelerating spiking neural networks with photonic reconfigurable devices
Lu, C., Xu, K., Liu, J., Ding, Y., Yu, J., Song, J., Meng, J., Wang, T., Guo, S., Jin, X., et al. (2026) · Nature Communications · doi:10.1038/s41467-026-72119-y · Cited by 3
Tsuda, K., Furutani, K., Yakubo, Y., Godo, H., Ando, Y., Kosuge, A., Nakura, T., & Yamazaki, S. (2024) · IEEE Journal of the Electron Devices Society · doi:10.1109/jeds.2024.3439712 · Cited by 3
“It will be necessary in the future to work on problems in higher levels such as CIFAR-100, or to construct reconfigurable networks to implement various types of NNs, when considering the practical application [35], [36], [37], [38].”
BackgroundHasler, J., & Basu, A. (2024) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/ad9b4a · Cited by 3
Giacomo, S. D., Ronchi, M., Amadori, M., Borghi, G., Carminati, M., & Fiorini, C. E. (2025) · IEEE Transactions on Radiation and Plasma Medical Sciences · doi:10.1109/trpms.2025.3530774 · Cited by 3
“Investigation on emerging memory technologies and devices for cross-point operations is the focus of many researches that include resistive switching RAM (RRAM, also known as memristors) [4], [5], [6], [7], [8], phase-change memory (PCM) [9], [10], [11], and ferroelectric capacitors [12], [13].”
A minimal dynamical system and analog circuit for non-associative learning
Smart, M., Shvartsman, S. Y., & Mönnigmann, M. (2024) · IEEE Conference on Decision and Control (CDC) · doi:10.1109/cdc56724.2024.10886642 · Cited by 3
Gao, K., Zhao, R., Li, X., Cai, J., Tong, H., & Miao, X. (2025) · Advanced Electronic Materials · doi:10.1002/aelm.202500032 · Cited by 3
A Scalable FPGA Architecture With Adaptive Memory Utilization for GEMM-Based Operations
Petropoulos, A., & Antonakopoulos, T. A. (2025) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2025.3571677 · Cited by 3
“A PPLICABILITY ON AN AIMC E MULATOR In this section, we outline how the proposed FPGA-based accelerator can be extended to emulate the noise characteristics of AIMC devices [16], enabling system accuracy assessment in DNNs.”
Self-citationEnergy efficiency and design challenges in analogue memristive chips
James, A. P. (2024) · Nature Reviews Electrical Engineering · doi:10.1038/s44287-023-00008-3 · Cited by 3
Synaptogen: A Cross-Domain Generative Device Model for Large-Scale Neuromorphic Circuit Design
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“This may limit the ability to simulate entire analog ML chips at once, but investigations are possible the level of individual cores, comprising, e.g., 256 × 256 devices [19], [20].”
Background‘Mind-blowing’ IBM chip speeds up AI
Castelvecchi, D. (2023) · Nature · doi:10.1038/d41586-023-03267-0 · Cited by 3
Voltage‐Summation‐Based Compute‐in‐Memory Technology with Capacitive Synaptic Devices
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Chen, Y., Li, X., Chen, Z., Tong, H., & Miao, X. (2025) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2025.3570683 · Cited by 3
“Transient tests revealed an average delay time of 70 ns, comparable to the measured performance of matrix–vector multiplications (MVMs) in IBM’s HERMES project chip [34].”
In-Memory Template Matching with Approximated PCC Computation Leveraging Memristive System
Tushar, S. N. B., Alam, S. H., Buchanan, G., Febbo, R., Das, H., & Rose, G. S. (2025) · International Symposium on Quality Electronic Design (ISQED) · doi:10.1109/isqed65160.2025.11014325 · Cited by 2
“Therefore, efforts are made to perform the most computationally expensive operations, such as matrix-vector multiplication, in an in-memory computing system, while handling other tasks in digital systems [3].”
Nie, S., Zang, M., Hao, D., Tang, L., Li, L., Liu, X., Zou, X., Miao, J., Shan, F., & Yang, Z. (2025) · ACS Applied Nano Materials · doi:10.1021/acsanm.5c02088 · Cited by 3
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Self-citationScaling Effects of Transistor Leakage Current and IR Drop on 1T1R Memory Arrays
Chen, J.-R., & Indiveri, G. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11043970 · Cited by 2
Şanlı, İ., Ferro, E., Vasilopoulos, A., Boesch, T., Sebastian, A., & Boybat, I. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11043396 · Cited by 2
“Re-quantization: DNN accelerators frequently support lower precision activations, particularly INT8 for energy and memory efficiency [12], and the communication fabric in AIMC-based accelerators are often customized for reduced precision data [2], [4].”
InfluentialSelf-citationEnergy-Efficient Training of Memristor Crossbar-Based Multi-Layer Neural Networks
Hasan, R., Alam, M. A., & Taha, T. M. (2025) · Chips · doi:10.3390/chips4030038 · Cited by 3
“IBM designed and fabricated a 64-core processing in-memory chip based on a phase-change memory device for the inference operation of deep neural networks [11].”
Solving All Eigenpairs With Resistive Memory-Based Analog Matrix Computing Circuits
Hong, C., Luo, Y., Zuo, P., Wang, S., & Sun, Z. (2025) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2025.3628178 · Cited by 2
“These arrays leverage highly scalable resistive memory technologies, such as resistive random-access memory (RRAM) [11], phase change memory (PCM) [12] and ferroelectric tunnel junction (FTJ) [13], to perform MVM in situ .”
Efficient Negative Weight Realization for Analog Nonlinear Resistive Neural Networks
Kiraz, Z., Pham, D. G., & Desgreys, P. (2025) · IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) · doi:10.1109/mwscas53549.2025.11244533 · Cited by 2
“Recent research on analog neural networks frequently employs memristor crossbar arrays for weight storage and matrix-vector multiplication [5], [9], [11]–[15].”
Beyond binary: multistate computing and neural systems with compound magnetic tunnel junctions
Koh, M. Z. X., Kumar, A., & Ho, P. (2025) · Journal of Physics D Applied Physics · doi:10.1088/1361-6463/ae27dc · Cited by 2
Yang, J., Luo, X., Ke, Y., Wang, Z., Shang, H., Dong, S., Fu, Z., Yang, X., Liu, H., & Basu, A. (2025) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3638445 · Cited by 2
“1(a) illustrates the normalized energy e ffi ciency (EE) based on input and weight resolutions and throughput of current RNN accelerators [19], [20], [21], [22], [23], [24], [25], [26], [27], [28] in comparison with those of recent CNN and MLP accelerators using CIM.”
InfluentialLin, Z., Wu, X., Chen, Z., Zhang, J., Deng, J., & Feng, Y. (2026) · iScience · doi:10.1016/j.isci.2026.114642 · Cited by 2
Bao, L., Zhao, J., Wang, Z., Zhang, H., Jiang, B., Ji, Y., Ji, Y., Sun, J., Yang, Y., Liang, L., et al. (2025) · Technical digest - International Electron Devices Meeting/Technical digest · doi:10.1109/iedm50572.2025.11353727 · Cited by 2
Kim, Y., Hur, N., Gim, H., Jeong, H., Suh, J., & Kwon, Y. (2026) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2026.3664333 · Cited by 2
“…and in-memory computing architectures, which eliminate the need for massive data transfer between the memory and processor, significantly reducing the computation time and power required for artificial intelligence methods such as deep learning and generative networks [10], [11], [12], [13], [14].”
Phase‐Change Memory for Cryogenic In‐Memory Computing
Lombardo, D., Gautam, S., Ferraris, A., Gallo, M. L., Bragaglia, V., Sebastian, A., & Sarwat, S. G. (2026) · Advanced Functional Materials · doi:10.1002/adfm.202525704 · Cited by 2
Self-citationA sub–10-millisecond neural dynamical system based on phase-change memristors
Cai, L., Tao, Y., Xie, C., Yan, L., Li, S. B., Shen, R., Pan, Z., Wang, X., Wang, B., Shi, D., et al. (2026) · Science · doi:10.1126/science.aee6277 · Cited by 2
Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited)
Burr, G. W., Narayanan, P., Ambrogio, S., Okazaki, A., Tsai, H.-Y. S., Hosokawa, K., Mackin, C., Nomura, A., Yasuda, T., Demarest, J. J., et al. (2023) · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · doi:10.23919/vlsitechnologyandcir57934.2023.10185411 · Cited by 2
“A second chip using 64 smaller (256 256) tiles has also been built and demonstrated [12].”
MethodSelf-citationD-SELD: Dataset-Scalable Exemplar LCA-Decoder
Takaghaj, S. M., & Sampson, J. (2024) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/ad9e2c · Cited by 2
“As the field of neuromorphic computing continues to advance, novel training methods are being investigated to harness the potential of SNNs in various neuromorphic platforms [2, 3, 4, 5, 6, 7, 8].”
BackgroundOn-chip Built-In Self-Calibration of Thermal Variations for Mixed-Signal In-Memory Computing
Singh, G. K., Numan, O., Monga, D. C., Andraud, M., & Halonen, K. A. I. (2024) · IEEE European Test Symposium (ETS) · doi:10.1109/ets61313.2024.10567960 · Cited by 2
“This motivates a large body of research on emerging architectures for IMC, building the IMC core with classical charge-based memories [3], or emerging memory technologies, for instance resistive memories such as resistive RAM (ReRAM) or phase change memories (PCM) [4].”
BackgroundAkkoç, S., Çınar, A., Ercan, B., Kalfa, M., & Arıkan, O. (2024) · Journal of the Franklin Institute · doi:10.1016/j.jfranklin.2024.107363 · Cited by 2
In-memory encryption using the advanced encryption standard
Kovats, T., Rameshan, N., Karunaratne, K. G., Giannopoulos, I., & Sebastian, A. (2025) · Philosophical Transactions of the Royal Society A Mathematical Physical and Engineering Sciences · doi:10.1098/rsta.2023.0396 · Cited by 2
Self-citationBe CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators
Zhao, S., Li, Y., Li, B., He, Y., Wang, M., Han, Y., & Wang, Y. (2025) · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · doi:10.1145/3676641.3716248 · Cited by 2
Liu, S., Sun, T., & Li, Y. (2025) · Science China Materials · doi:10.1007/s40843-025-3342-5 · Cited by 2
TRIM: Thermal Auto-Compensation for Resistive In-Memory Computing
Monga, D. C., Singh, G., Numan, O., Adam, K., Andraud, M., & Halonen, K. A. I. (2025) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2025.3586889 · Cited by 3
“Obtaining a variable conductance can be done using multiple resistive technologies, in CMOS or with emerging nonvolatile memories (eNVM) such as resistive RAMs (ReRAMs), Magnetic RAMs (MRAMs), or phase change memories (PCMs) [5], [6], [7].”
Sakemi, Y., Okamoto, Y., Morie, T., Nobukawa, S., Hosomi, T., & Aihara, K. (2025) · Advanced Intelligent Systems · doi:10.1002/aisy.202500351 · Cited by 2
Kaiser, M. A.-A., Sunder, S., Jacob, A. P., & Jaiswal, A. (2025) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1109/dac63849.2025.11132453 · Cited by 2
Akhtar, M. S. (2025) · AppliedMath · doi:10.3390/appliedmath5040145 · Cited by 2
Efficient transformer adaptation for analog in-memory computing via low-rank adapters
Li, C., Ferro, E., Lammie, C., Gallo, M. L., Boybat, I., & Rajendran, B. (2026) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/ae405e · Cited by 4
“Despite this small proportion of trainable parameters, the model demonstrates strong robustness to hardware constraints, as indicated by F 1 and EM scores that are on par with conventional AHWA training.”
InfluentialA Memcomputing Approach to Prime Factorization
Sharp, T. A., Khare, R., Pederson, E., & Traversa, F. L. (2023) · IEEE International Conference on Rebooting Computing (ICRC) · doi:10.1109/icrc60800.2023.10386235 · Cited by 2
“In the pursuit of mitigating the von Neumann bottleneck, the concept of near-memory computing [21] has emerged as a promising approach, closely related to in-memory computing [22], [23], [24], [25], [26], [27].”
BackgroundWhich Coupled is Best Coupled? An Exploration of AIMC Tile Interfaces and Load Balancing for CNNs
Klein, J. A. H., Boybat, I., Ansaloni, G., Zapater, M., & Atienza, D. (2024) · IEEE Transactions on Parallel and Distributed Systems · doi:10.1109/tpds.2024.3437657 · Cited by 1
“In these systems, AIMC clusters are placed far away from the CPU and use a bus-based interface, which incurs a much higher data transaction cost, at the benefit of having more area to expand accelerator capability, usually in the form of larger and more numerous crossbars [13], [16], [18], [26].”
BackgroundMethodInfluentialCapacitance and Conductance Compensation Methods for Efficient Computing‐In‐Memory Designs
Luo, Y., Qiao, F., & Sun, Z. (2024) · Advanced Electronic Materials · doi:10.1002/aelm.202400452 · Cited by 1
Pang, H., Cappetta, C., Massa, R., Vasilopoulos, A., Ferro, E., İslamoğlu, G., Garofalo, A., Conti, F., Luca Benini, C., Boybat, I., et al. (2025) · Design, Automation, and Test in Europe · doi:10.23919/date64628.2025.10992944 · Cited by 1
“Multiple AIMC tiles are often employed on AIMC-based DNN accelerators to maximize the on-chip weight capacity [1], [2].”
Self-citationPark, M., Chien, H.-T., Chen, W.-C., Mimi, A. A., Wan, W., Woo, K. S., Yi, S., & Kumar, S. (2025) · npj Unconventional Computing · doi:10.1038/s44335-025-00035-3 · Cited by 2
Metadata
- Authors
- Le Gallo, M., Khaddam-Aljameh, R., Stanisavljevic, M., Vasilopoulos, A., Kersting, B., Dazzi, M., Karunaratne, G., Brändli, M., Singh, A., Müller, S. M., Büchel, J., Timoneda, X., Joshi, V., Rasch, M. J., Egger, U., Garofalo, A., Petropoulos, A., Antonakopoulos, T., Brew, K., Choi, S., Ok, I., Philip, T., Chan, V., Silvestre, C., Ahsan, I., Saulnier, N., Narayanan, V., Francese, P. A., Eleftheriou, E., & Sebastian, A.
- Affiliations
- IBM Research - Zurich (CH)
- IBM (Germany) (DE)
- IBM (United States) (US)
- University of Patras (GR)
- IBM Research - Albany (US)
- Corresponding author
- Sebastian, Abu
- ORCID
- Le Gallo, Manuel
- Khaddam-Aljameh, Riduan
- Vasilopoulos, Athanasios
- Kersting, Benedikt
- Dazzi, Martino
- Karunaratne, Geethan
- Singh, Abhairaj
- Büchel, Julian
- Timoneda, Xavier
- Joshi, Vinay
- Rasch, Malte J.
- Garofalo, Angelo
- Petropoulos, Anastasios
- Antonakopoulos, Theodore
- Brew, Kevin
- Philip, Timothy
- Chan, Victor
- Saulnier, Nicole
- Narayanan, Vijay
- Francese, Pier Andrea
- Sebastian, Abu
- Venue
- Nature Electronics
- Published
- 2023-08-10
- Volume
- 6
- Issue
- 9
- Pages
- 680-693
- ISSN
- 2520-1131 (ISSN-L)
- OpenAlex
- W4385896568
- Semantic Scholar
- e28c05440f28c2092a251cf413f2a9d3c90fd1bb
- Cited by
- 310
- References
- 49
- Citations by year
- 2026: 78 · 2025: 130 · 2024: 79 · 2023: 23
- FWCI
- 23.00
- Type
- journal article
- Language
- en
- Open access
- green
- arxiv.org
- Licence
- Locations
- Nature Electronics (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna) (submittedVersion, other-oa)
- arXiv (Cornell University) (cc-by)
- Funders
- European Commission (HORIZON2020, 682675)
- H2020 European Research Council (966764)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Analog and Mixed-Signal Circuit Design
- Keywords
- phase-change memory, deep neural network inference, network-on-chip, ResNet, energy efficiency, resistive memory devices
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
A language model drew the claims from the paper on 2026-10-07, under version 3 of the claim definition (model deepseek-v4.1-flash, prompt extract-v3).
A second model labelled each claim on 2026-10-07 (model jev-1.13-20260917, definition revision gold-guideline-v0.2).
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
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