Four-dimensional address topology for circuits with stacked multilayer crossbar arrays
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We present a topological framework that provides a simple yet powerful electronic circuit architecture for constructing and using multilayer crossbar arrays, allowing a significantly increased integration density of memristive crosspoint devices beyond the scaling limits of lateral feature sizes. The truly remarkable feature of such circuits, which is an extension of the CMOL (Cmos + MOLecular-scale devices) concept for an area-like interface to a three-dimensional system, is that a large-feature-size complimentary metal-oxide-semiconductor (CMOS) substrate can provide high-density interconnects to multiple crossbar layers through a single set of vertical vias. The physical locations of the memristive devices are mapped to a four-dimensional logical address space such that unique access from the CMOS substrate is provided to every device in a stacked array of crossbars. This hybrid architecture is compatible with digital memories, field-programmable gate arrays, and biologically inspired adaptive networks and with state-of-the-art integrated circuit foundries.
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Eq. (4) can be seen as a modification of the Duffing oscillator equation, whose chaotic properties are well-known.
“Generally, Eq. (4) can be seen as a modification of the Duffing oscillator equation, whose chaotic properties are well-known 16 .”
From Bistable Nonvolatile Elastic-Membrane Memcapacitor Exhibiting a Chaotic Behavior (2011) · cites this paper as [16]
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The 3-D Stacking Bipolar RRAM for High Density
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Memristors for neural branch prediction
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Stateful logic pipeline architecture
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An Integrated Optimization Approach for Nanohybrid Circuit Cell Mapping
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A Study of the Memristor Models and Applications
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Architecting energy efficient crossbar-based memristive random-access memories
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Low Complexity Two-Dimensional Weight-Constrained Codes
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Novel techniques for memristive multifunction logic design
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Memory Technologies for Neural Networks
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Memristors and Memristive Devices for Neuromorphic Computing
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Stateful Memristor-Based Search Architecture
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Monolithically stackable hybrid FPGA
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Low complexity two-dimensional weight-constrained codes
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- Authors
- Strukov, D. B., & Williams, R. S.
- Affiliations
- Hewlett-Packard (United States) (US)
- Venue
- Proceedings of the National Academy of Sciences
- Publisher
- National Academy of Sciences
- Published
- 2009-12
- Volume
- 106
- Issue
- 48
- Pages
- 20155-20158
- ISSN
- 0027-8424 (ISSN-L)
- 1091-6490
- PMC
- PMC2777961
- OpenAlex
- W2031176269
- Cited by
- 153
- References
- 27
- Citations by year
- 2026: 1 · 2025: 2 · 2024: 2 · 2023: 4 · 2022: 5 · 2021: 10 · 2020: 7 · 2019: 6 · 2018: 9 · 2017: 8 · 2016: 8 · 2015: 10 · 2014: 9 · 2013: 18 · 2012: 17
- FWCI
- 14.02
- Type
- journal article
- Language
- en
- Open access
- green
- www.ncbi.nlm.nih.gov
- Locations
- Proceedings of the National Academy of Sciences (publishedVersion)
- PubMed Central (publishedVersion)
- PubMed (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › 3D IC and TSV technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
- Keywords
- CMOS substrate, vertical interconnects, integration density, neuromorphic hardware
- MeSH terms
- Computer Systems, Electronics, Semiconductors, Electric Impedance
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