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16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips
Abstract
Recent SRAM-based computation-in-memory (CIM) macros enable mid-to-high precision multiply-and-accumulate (MAC) operations with improved energy efficiency using ultra-small/small capacity (0.4-8KB) memory devices. However, advanced CIM-based edge-AI chips favor multiple mid/large capacity SRAM-CIM macros: with high input (IN) and weight (W) precision to reduce the frequency of data reloads from external DRAM, and to avoid the need for additional SRAM buffers or ultra-large on-chip weight buffers. However, enlarging memory capacity and throughput increases the delay parasitics on WLs and BLs, and the number of parallel computing elements; resulting in longer compute latency (tAC), lower energy-efficiency (EF), degraded signal margin, and larger fluctuations in power consumption across data-patterns (see Fig. 16.3.1). Recent SRAM-CIM macros tend to not use in-lab SRAM cells, with a logic-based layout, in favor of foundry provided compact-layout 8T [2], 3, [5] or 6T cells with local-computing cells (LCCs) [4], [6] to reduce the cell-array area and facilitate manufacturing. This paper presents a SRAM-CIM structure using (1) a segmented-BL charge-sharing (SBCS) scheme for MAC operations, with low energy consumption and a consistently high signal margin across MAC values (MACV); (2) An new LCC cell, called a source-injection local-multiplication cell (SILMC), to support the SBCS scheme with a consistent signal margin against transistor process variation; and (3) A prioritized-hybrid-ADC (Ph-ADC) to achieve a small area and power overhead for analog readout. A 28nm 384kb SRAM-CIM macro was fabricated using a foundry compact-6T cell with support for MAC operations with 16 accumulations of 8b-inputs and 8b-weights with near-full precision output (20b). This macro achieves a 7.2ns tACand a 22.75TOPS/W EF for 8b-MAC operations with an FoM (IN-precision × W-precision × output-ratio × output-channel × EF/tAC) 6× higher than prior work.
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“Although several compute-in-memory or near-memory approaches based on SRAMs and digital compute35–38 have been presented in the literature, most of these do not address the energy and time costs of reloading weights, thus making direct side-by-side comparisons against NVM-based weight-stationary approaches difficult.”
From An analog-AI chip for energy-efficient speech recognition and transcription (2023) · cites this paper as [38]
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- 10.1109/ISSCC.2019.8662392 · DOI
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Items 101–179 of 179
Dorzhigulov, A., & Saxena, V. (2023) · Frontiers in Neuroscience · doi:10.3389/fnins.2023.1177592 · Cited by 6
“While in-memory computing prototypes utilize volatile DRAM and SRAMmemories (Su et al., 2021; Xie et al., 2021), realizing it in NVM arrays is desirable to implement persistent weights and higher weight density.”
MethodTsai, Y.-C., Ting, W.-C., Wang, C., Chang, C., & Liu, R.-S. (2023) · Design, Automation, and Test in Europe · doi:10.23919/date56975.2023.10137074 · Cited by 4
“Recently, computing in memory (CIM) [1]–[3] has been an emerging architecture for convolutional neural networks (CNNs).”
BackgroundSelf-citationKim, J., Lee, K., & Park, J. (2022) · International Symposium on Low Power Electronics and Design (ISLPED) · doi:10.1145/3531437.3539718 · Cited by 5
“When the MSB is ‘0’, the next 3-bit flash ADC sampling occurs on the lower pMAC range (from 0 to 63) using ABLREF[1] ~ ABLREF[7].”
InfluentialWang, X., Liu, X., Hu, X., Zhong, X., Chen, X., Liu, Y., Kong, P., Tian, F., & Tsui, C.-Y. (2022) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas54282.2022.9869970 · Cited by 5
“A prioritized hybrid-ADC in [2] can save energy and area by combining a successive-approximation ADC (SAR-ADC) and a single slope ADC (SS-ADC).”
BackgroundMethodWang, Y., He, Z., Zhao, C., Wu, Z., Gao, M., Han, H.-M., Wei, S.-J., Hu, Y., Tu, F.-B., & Yin, S.-Y. (2026) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3566283 · Cited by 4
“…instead of using analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) to perform analog MAC like conventional analog CIM [22], [30], [34], the digital CIM works usually customize each SRAM cell with an additional two-input NOR for bitwise multiplication and place digital…”
Cao, W., Gao, J., Xin, X., & Zhang, X. (2024) · Design Automation Conference · doi:10.1145/3649329.3655930 · Cited by 4
“In particular, it has shown remarkable energy efficiency in accelerating a variety of machine learning tasks, ranging from image classification and object recognition to natural language processing [14, 16, 19, 21].”
InfluentialFP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC
Gajawada, S., Gupta, A., Prasad, K., & Mekie, J. (2024) · International Conference on VLSI Design · doi:10.1109/vlsid60093.2024.00046 · Cited by 4
“Other researchers have pursued a hybrid IMC approach that combines digital and analog circuits for in-memory computation [9] [10].”
BackgroundThree Challenges in ReRAM-Based Process-In-Memory for Neural Network
Yang, Z., Liu, K., Duan, Y., Fan, M., Zhang, Q., & Jin, Z. (2023) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas57966.2023.10168640 · Cited by 3
Lo, Y.-C., Yeh, C.-C., Wu, J.-S., Wang, C., Tsai, Y.-C., Ting, W.-C., & Liu, R.-S. (2022) · International Conference on Computer Aided Design · doi:10.1145/3508352.3549333 · Cited by 4
Self-citationA 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications
Zhou, K., Lin, R., Guo, Z., Liu, Y., Jiang, J., Zhao, C., Fang, J., Xu, X., Xue, X., & Zeng, X. (2022) · Microelectronics Journal · doi:10.1016/j.mejo.2022.105478 · Cited by 4
FeFET-Based Analog In-Memory Computing With Inherent Shift-and-Add Capability
Yang, Z., Huang, Q., Qian, Y., Cai, J., Zhou, M., Ni, K., Kämpfe, T., Yan, Z., Yin, X., & Zhuo, C. (2026) · IEEE Transactions on Computers · doi:10.1109/tc.2026.3662915 · Cited by 3
“9(k), the corresponding capacitance discharge rate on BL[1] is also four times that on BL[0]/BL[2], which aligns with the weight bit significance.”
InfluentialAn 8-bit Precision 10T SRAM Compute-in-Memory Macro Using ADC With Small Area
Chen, T., Zhuang, H.-Y., He, Y.-J., & Li, Q. (2026) · IEEE Transactions on Circuits and Systems - II - Express Briefs · doi:10.1109/tcsii.2025.3639896 · Cited by 3
“To achieve these goals, di ff erent CIM structures have been reported in recent years [2], [3], [4], [5], [6], [7], [8].”
Xue, C., Yang, Y., He, S., Du, G., Wang, Y., & He, Y. (2025) · IEEE Transactions on Circuits and Systems I Regular Papers · doi:10.1109/tcsi.2025.3582263 · Cited by 3
“The majority of contemporary CIM research endeavors have primarily focused on optimizing integer MAC operations [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24].”
Zhao, Y., Wang, Y., Wang, Y.-H., Xie, H., Zhu, Y., Martins, R. P., Chan, C.-H., Yin, S.-Y., & Zhang, M.-L. (2025) · IEEE Custom Integrated Circuits Conference · doi:10.1109/cicc63670.2025.10982876 · Cited by 3
Cambricon-M: A Fibonacci-Coded Charge-Domain SRAM-Based CIM Accelerator for DNN Inference
Guo, H., Zou, M., Hao, Y., Du, Z., Ren, E., Liu, Y., Zhao, Y., Ma, T., Zhang, R., Hu, X., et al. (2024) · IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1109/micro61859.2024.00121 · Cited by 3
“For example, J.W. Su et al. [53] designs a charge-domain SRAM-CIM with dedicated multiplication cell and priority-hybrid ADC, achieving 22.75 TOPS/W energy efficiency for 8 b DNN; Jia et al. [21] proposes a programmable SRAM-CIM accelerator, achieving 121 TOPS/W for 4 b DNN; S.E. Hsieh et al. [18]…”
InfluentialISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory
Lo, Y.-C., Wu, J.-S., Wang, C., Tsai, Y.-C., Yeh, C.-C., Ting, W.-C., & Liu, R.-S. (2024) · IEEE Transactions on Computers · doi:10.1109/tc.2024.3404060 · Cited by 2
“We collect recent silicon-verified CIM macros and summarize their specification, including the number of inputs, bitwidth for each input, and the number of bitlines [2], [12], [13], [23], [24] for practically considering ISSA architecture.”
BackgroundMethodInfluentialSelf-citationZhou, H., Hong, H., Liu, D., Liu, H., Xia, Y., Li, K., Liu, J., Luo, S., Mao, W., & Yu, H. (2023) · IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) · doi:10.1109/aicas57966.2023.10168630 · Cited by 3
“Previous works of [7], [9]–[11] are used as benchmarks for energy efficiency comparison.”
BackgroundMethodReliable Computing of ReRAM Based Compute-in-Memory Circuits for AI Edge Devices
Chang, M., Hung, J.-M., Chen, P.-C., & Wen, T.-H. (2022) · International Conference on Computer Aided Design · doi:10.1145/3508352.3561119 · Cited by 2
Self-citationDesign Methodology and Trends of SRAM-Based Compute-in-Memory Circuits
Dong, F., Si, X., & Chang, M. (2022) · IEEE International Conference on Solid-State and Integrated Circuit Technology · doi:10.1109/icsict55466.2022.9963239 · Cited by 3
“The MAC operations in CIM macros are commonly performed through either current domain [15, 16, 22, 23, 29, 37, 40, 41, 44, 47], time domain [18, 32, 46, 54] or charge domain [13, 14, 21, 24, 27, 28, 51, 55-57].”
BackgroundSelf-citationXiao, K., Cui, X., Qiao, X., Pan, N., Wang, X., & Wang, Y. (2022) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas48785.2022.9937963 · Cited by 6
“Previous work ISSCC20[9] JSSC20[10] VLSI21[11] ISSCC21[12] ISCAS21[13] This work Technology 7nm-FinFET 65nm 28nm 28nm 65nm 28nm Macro size 4kb 16kb 288kb 384kb 16kb 32kb Bit-cell area(μm(2)) 0.”
Qiao, X., Yang, Y., Song, J., Wei, R., Tang, X., Li, M., Wang, R. S., & Wang, Y. (2026) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2026.3651775 · Cited by 2
“It enables low-power execution of numerous multiply-and-accumulate (MAC) operations [1], [2], [3], [4], [5], [6], [7], [8], [9].”
Mori, H., Hung, J.-M., Zhao, W.-C., Khare, K., Crafton, B., Ishii, H., Lee, C.-E., Peng, X., Sun, X., Fujino, Y., et al. (2026) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2025.3646072 · Cited by 2
“Recent works examined the trade-o ff s among multiply-accumulate (MAC)throughput, energy e ffi ciency, and accuracy in analog-based or analog-digital mixed CIM designs [1], [2], [3].”
Zhang, J., Tong, Z., Zhao, Q., Peng, C., Lu, W., Zhou, J., Chen, X., Lin, Z., & Wu, X. (2026) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2026.3657208 · Cited by 1
“…modules to enhance dot-product computation [3]; Si et al. [30] utilized additional local computing cells for 8-bit MAC; Su et al. [31], [32] proposed two approaches: transpose multiple cells and source-injection local-multiple cells for multibit MAC; Agrawal et al. [33] implemented a…”
Guo, H., Ma, T., Du, Z., Zou, M., Hao, Y., Zhao, Y., Zhang, R., Li, W., Hu, X., XU, Z., et al. (2026) · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · doi:10.1109/hpca68181.2026.11408520
“For example, Su et al. [40] design a 384kb 6T-SRAM charge-domain SRAM-CIM macro for edge DNN inference, achieving 22.75 TOPS/W; Delta-Sigma CIM [5] exploits the similarity between consecutive 1-bit slices with differential computing, achieving 21.38 TOPS/W; Jia et al. [19] propose a programmable…”
InfluentialShaban, A. S., Gothalyan, S., Suri, M., & Hou, T. (2025) · IEEE transactions on circuits and systems for artificial intelligence. · doi:10.1109/tcasai.2025.3592864 · Cited by 2
“Conventional, SRAM based [5], [6], [7], [8], [9] INT precision CIM accelerators have been explored in literature for inference on edge devices.”
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation
Xiong, T., Ye, Y., Si, X., & Yang, J. (2024) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2024.3439355 · Cited by 1
“Vector A from the shared global buffer is boosted by the local MAC stage and input to MCS without requiring multilevel LDO [31] or pulse modulation circuits [15].”
Self-citationZhao, R., Gong, Z., Liu, Y., & Chen, J. (2024) · Micromachines · doi:10.3390/mi15050617 · Cited by 1
Pu, X.-Y., Zhang, Y.-R., Guo, A., Zhang, Z.-Y., He, S.-N., & Si, X. (2023) · Journal of Physics, Conference Series · doi:10.1088/1742-6596/2524/1/012033 · Cited by 2
Self-citationHong, S., Um, S., Kim, S., Kim, S., Jo, W., & Yoo, H. (2023) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas46773.2023.10181902 · Cited by 2
“Analog computing-in-memory (CIM) [1-5] has achieved a breakthrough in deep neural network (DNN) accelerators by supporting energy-efficient multiply-accumulate (MAC) operations, which dominate DNN workloads.”
BackgroundMethodInfluentialHadamard product-based in-memory computing design for floating point neural network training
Fan, A., Fu, Y., Tao, Y., Jin, Z., Han, H., Liu, H., Zhang, Y., Yan, B., Yang, Y., & Huang, R. (2023) · Neuromorphic Computing and Engineering · doi:10.1088/2634-4386/acbab9 · Cited by 3
“With these advantages, SRAM emerges as one of the most promising memory technology for IMC as the CMOS technology down-scaling becomes harder than ever [24].”
BackgroundIPOCIM: Artificial Intelligent Processor with Adaptive Ping-pong Computing-in-Memory Architecture
Chang, L., Li, C., Zhao, X., Lin, S., & Zhou, J. (2022) · IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) · doi:10.1109/icta56932.2022.9963134 · Cited by 1
“A potential solution is computing-in-memory (CIM) architecture to combine the memory and computation functions, where the memory array can support high parallel computation operations [4].”
BackgroundPseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes
Kim, S., & Park, J.-E. (2022) · Sensors · doi:10.3390/s22114284 · Cited by 4
“Many studies have implemented PIM based on static random-access memory (SRAM) due to its logic compatibility and high operation speed [1–7].”
BackgroundA 12TOPS/W Computing-in-Memory Accelerator for Convolutional Neural Networks
Fu, J.-H., & Chang, S.-J. (2022) · International Symposium on Circuits and Systems · doi:10.1109/iscas48785.2022.9937467 · Cited by 2
Self-citationChallenges of Computation-in-Memory Circuits for AI Edge Applications
Jhang, C.-J., Chen, P.-C., & Chang, M. (2021) · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · doi:10.1109/vlsi-tsa51926.2021.9440045 · Cited by 5
“CIM can be applied to static random-access memory (SRAM-CIM) [1]-[23] or non-volatile memory (nvCIM) [24]-[38].”
BackgroundSelf-citationShiba, K., Zhan, Z., Nii, K., Wang, Y., Chang, T.-Y. J., Kosuge, A., Hamada, M., & Kuroda, T. (2026) · IEEE Transactions on Circuits and Systems Part 1: Regular Papers · doi:10.1109/tcsi.2026.3672648 · Cited by 1
“Compute-in-memory (CIM) solves these problems by integrating the compute circuits inside the memory [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19].”
Readout scheme in analog computing-in-memory: Review of design principles and recent progress
Zhang, S., Huang, P., You, H., Wu, X., Chen, W., Zhang, L., & Cui, Q. (2026) · Microelectronic Engineering · doi:10.1016/j.mee.2026.112466
An LSGQ-FFS Framework for Adaptive Optimization of Hybrid INT-CIM Architecture
Li, S.-C., Chen, X., Xiong, Y., Liu, Y., Kong, L.-Y., Wang, H., Jiao, T.-H., Wang, X., Li, X., Yan, Y., et al. (2026) · IEEE Transactions on Very Large Scale Integration (vlsi) Systems · doi:10.1109/tvlsi.2025.3627654 · Cited by 1
“Most CIM macros already use or can be converted INT formats because INT inference performs well and fits fixed-point CIM architectures [6].”
Self-citation4T Bitcell for Digital Compute-in-Memory
Freye, F., Lanius, C., Mutert, N., & Gemmeke, T. (2025) · IEEE Nordic Circuits and Systems Conference · doi:10.1109/norcas66540.2025.11231198 · Cited by 1
GEBA: Gradient-Error-Based Approximation of Activation Functions
Ye, C., & Jeong, D. S. (2023) · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · doi:10.1109/jetcas.2023.3328890 · Cited by 1
“C OMPUTING-IN-MEMORY (CIM) is a scheme to accelerate the major operations of deep learning (DL), i.e., multiply-accumulate (MAC) operations, at low-power consumption [1], [2], [3], [4].”
BackgroundWang, C.-C., Lo, Y.-C., Wu, J.-S., Tsai, Y.-C., Chang, C.-C., Hsu, T.-W., Chu, M.-W., Lai, C.-Y., & Liu, R.-S. (2023) · ICCD · doi:10.1109/iccd58817.2023.00085 · Cited by 1
“To improve the performance of neural network computations on edge devices, many researchers have turned to computing-in-memory (CIM) solutions that perform in-situ computations within memory units [5]–[7].”
BackgroundSelf-citationWang, X.-M., Tian, F.-S., Chen, X.-Z., Zheng, J., Liu, X., Tu, F.-B., Yang, J., Sawan, M., Cheng, K.-T., & Tsui, C.-Y. (2023) · arXiv.org · doi:10.48550/arxiv.2307.05944 · Cited by 1
Yin, G., Zhou, M., Chen, Y., Tang, W., Yang, Z., Lee, M., Du, X., Yue, J., Liu, J., Yang, H., et al. (2022) · arXiv (Cornell University) · doi:10.48550/arxiv.2212.04320 · Cited by 1
“This A/D conversion needs to be accurate so as to avoid excessive distortion in the subsequent shift-and-add of the CiM outputs, resulting in immense ADC-related overheads during the trade-off between power, area, and latency [2][8].”
BackgroundA Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model
Feng, Z., Wang, B., Zhang, Z.-Y., Guo, A., & Si, X. (2022) · Asia Pacific Conference on Circuits and Systems · doi:10.1109/apccas55924.2022.10090256 · Cited by 1
“However, most of the previous work in the analog domain is mainly applicable to low-precision situations, such as Xin Si[1], Z.jiang[2], J.-W.Su[3].”
Self-citationWang, L., An, J., Ye, W., Li, W., Gao, H., He, Y., Gao, J., Yue, J., Fan, L., & Dou, C. (2022) · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · doi:10.1109/apccas55924.2022.10090254 · Cited by 1
“Furthermore the charge-domain CIMs, based on capacitive charge sharing [10][11] or charge coupling [12][13], can eliminate the DC current paths during computing (Fig.”
BackgroundPipelined Computing-in-Memory Macro with Computation-Memory Aware Technique
Chang, L., Zhao, P., & Zhou, J. (2022) · Asia Pacific Conference on Circuits and Systems · doi:10.1109/apccas55924.2022.10090333 · Cited by 1
Xiao, K., Cui, X., Qiao, X., Wang, X., & Wang, Y. (2022) · IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) · doi:10.1109/icta56932.2022.9962978 · Cited by 2
“Works[1]-[6] tried to improve the flexibility of CIM.”
BackgroundZhao, Q., Jiang, F.-G., Yang, Y., Ge, J.-T., Long, M., Duan, C.-L., & Lin, Z.-T. (2026) · IEEE Transactions on Very Large Scale Integration (vlsi) Systems · doi:10.1109/tvlsi.2026.3731472
“1(a), the von Neumann architecture—characterized by its segregated memory and computation units—encounters memory and power walls during highly parallel MAC processing [1], [2], [3], [4], [5].”
Lu, W., Tan, L., Xue, T., Peng, C., Lin, Z., & Wu, X. (2026) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2026.3717001
Yuan, Y., Sun, Z., Yang, Y., Wang, X., Li, X., Ma, C., Chen, Q., Tang, M., Wei, X., Wu, H., et al. (2026) · IEEE Journal of Solid-State Circuits · doi:10.1109/jssc.2026.3668132
“…physical quantities such as current or charge to embody data by utilizing the properties of the devices in the CIM macro circuits, which generally can achieve high energy e ffi ciency but su ff er from accuracy loss due to process, voltage, and temperature (PVT) variations [15], [16], [17], [18].”
Yan, S., Wang, J. J., Liu, S., Liu, Y., Wang, Y., Wu, Z. Q., Mao, H. D., Wang, X. R., Chen, T., & Liu, Y. (2026) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2026.3689104
“For larger matrix operations, this modular design scales through a tiling strategy, balancing throughput and area e ffi ciency [13], [14].”
Jo, Y.-J., Yang, C., Cao, S., Yoon, D.-H., Zheng, Y.-J., & Kim, T. T.-H. (2026) · IEEE Transactions on Circuits and Systems Part 1: Regular Papers · doi:10.1109/tcsi.2026.3677534
“Flash-type [26], [27], single-slope [6], and SAR with single-slope hybrid type [7], [28] can also be employed. itcells can be broadly classified into two categories depending on how multiply-and-accumulation (MAC) is implemented: current-mode [21], [23], [29], [30] and charge-mode [22], [31], [32],…”
Improving robustness and variability tolerance in SRAM-based in-memory computing using body bias
Gupta, N., Acharya, L. C., Singh, K. J., Dargupally, M., Acharya, A., Dasgupta, S., & Bulusu, A. (2026) · Semiconductor Science and Technology · doi:10.1088/1361-6641/ae887f
“In charge-based MAC operations [7–11], capacitors are used with 6T (or 6T + decoupled ports) bitcells to store the MAC output via charge sharing.”
Hariprasad, S., Balasubramanian, S., Patel, A. A., & Choi, K. (2026) · Electronics · doi:10.3390/electronics15122630
A Multiplication-Free Floating-Point CIM Architecture with a 5-Bit Approximate Squaring Circuit
Li, X., Ge, J.-T., Long, M., Jiang, F.-G., Duan, C.-L., Yang, Y., Zhang, W., Liu, Y., Zhang, B., & Lin, Z.-T. (2026) · International Symposium on Circuits and Systems · doi:10.1109/iscas66217.2026.11562926
Bansal, S., Hogganvik, P. G., Jain, S., Hota, G., Cherif, B., Leugering, J., & Cauwenberghs, G. (2026) · International Symposium on Circuits and Systems · doi:10.1109/iscas66217.2026.11562109
“Peripheral components such as ADCs and JSSC’21[9] ISSCC’21[10] JSSC’22[11] ISCAS’23[12] ISSCC’07[8]”
Clipping Error Compensation for Accuracy Recovery and Throughput Improvement in Computing-in-Memory
Tsai, Y.-C., Shen, H.-H., & Liu, R.-S. (2026) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas66217.2026.11562334
Self-citationGong, Q., Staszewski, R., Al-Hashimi, B. M., & Xu, K. (2026) · International Symposium on Circuits and Systems · doi:10.1109/iscas66217.2026.11562773
ELSA: An Elastic Snn Inference Architecture for Efficient Neuromorphic Computing
You, K., Nie, C., Yan, L. J., Wei, Z., Zou, C., Xu, Z., Feng, Y., Jiang, H., & He, Z. (2026) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1109/isca66397.2026.00178
“All designs are evaluated with the voltage of 0.9 V. Eyeriss † [21] Eyeriss v2 ‡ [34] ANT[18] S-CONV[35] AIOQAB[36] Sanger[37] ViTALiTy[38] AEC-CIM[39] LLH-CIM[40] ELSA [41]; : ViT-S on ELSA is trained by ourselves, while other accuracies are taken from original work.”
InfluentialLu, W., Tan, L., Wang, S., Xue, T., Peng, C., Lin, Z., & Wu, X. (2026) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2026.3668021
“To address this fundamental limitation, computing-in-memory (CIM) has emerged as a promising paradigm by enabling parallel data processing within memory modules, thereby mitigating the von Neumann bottleneck and improving overall system e ffi ciency [2], [3], [4], [5].”
Wan, T., Cao, Y. K., Yang, H., & Li, X. (2026) · Design, Automation, and Test in Europe · doi:10.23919/date69613.2026.11539370
“However, efficiently deploying unstructured sparse models onto CiM architectures [4]–[8] remains challenging, as CiM relies on dense, regular data layouts to achieve high throughput and energy efficiency, as show in Fig.”
MIRAGE:MRAM-Based Near ADC-Less Compute-In-Memory Macro for Deep Learning Acceleration
Mukherjee, M., Pranta, A. B., Saxena, U., Mukherjee, A., Sharma, D., Gaurav Kumar, K., & Roy, K. (2026) · Design, Automation, and Test in Europe · doi:10.23919/date69613.2026.11539274
Analysis of an Efficient CIM-SRAM for VLSI Applications
Mohamed Fawaz., D., M, D., Sowmiya, G., Aswin, B., S, R., & Dashwanth, P. (2026) · 2026 International Conference on Connected Intelligence for Industrial Applications (CI2A) · doi:10.1109/ci2a69097.2026.11576891
“Su et al.Presented a 28-nm 6T SRAM CIM macro with 8-bit precision, showing that the standard SRAM arrays can be opted for in-memory MAC operations without doing any significant cell modification[3].”
Lu, W., Liu, H., Meng, K., Gong, X., Wang, Z., Hu, W. S., Peng, C., Gao, S., Lin, Z., & Wu, X. (2025) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2025.3619502
“The computing-in-memory (CIM) architecture eliminates bottle-necks by integrating multiply–accumulate (MAC) operations into memory, such as static random access memory (SRAM) [1], [2], [3] and resistive RAM (ReRAM) [4], [5], [6].”
You, A., Ren, E., Fang, D. Z., Qu, C., Luo, L., Guo, H., Wei, Q., Liu, X.-J., & Qiao, F. (2025) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2025.3570135 · Cited by 1
“The PEs employ the design proposed in [35] and Fig.”
Low-Rank Compensation in Hybrid 3D-RRAM/SRAM Computing-in-Memory System for Edge Computing
Tang, W., Nie, L., Ma, C., Wu, H., Yuan, Y., Zhang, S., Liu, Q., & Zhang, F. (2025) · Eng—Advances in Engineering · doi:10.3390/eng6120332
“Currently, most CIM-based works use either emerging non-volatile memories, such as RRAM and MRAM, or volatile SRAM for neural network acceleration [4–6].”
DMP-BFP: Dynamic Mixed-Precision Block Floating-Point and Exponent-Guided Precision Adjustment
Tsai, Y.-C., Chang, C.-C., & Liu, R.-S. (2025) · IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) · doi:10.1109/iccd65941.2025.00012
“Consequently, various research efforts have focused on improving the energy efficiency of large-scale convolution operations, with approaches including mixed-precision techniques [1], [2], data sparsity [3], [4], computing architecture [5], [6], and novel datatype [7], [8].”
Self-citationLin, Z.-T., Yang, Y., Long, M., Li, H., Li, R., Zhang, W., Wang, X., Zhao, Q., Wu, X.-L., & Liu, Y. (2025) · Asia Pacific Conference on Circuits and Systems · doi:10.1109/apccas67402.2025.11377366
Liu, Y., Li, H., Yue, C., Wu, X.-L., Peng, C.-Y., Lu, W.-J., Dai, C.-H., Li, X., & Lin, Z.-T. (2025) · Asia Pacific Conference on Circuits and Systems · doi:10.1109/apccas67402.2025.11378321
“Current mainstream CIM architectures primarily target fixed-point or integer operations [3][4], suffering from intrinsic limitations in dynamic range and computational precision.”
SRAM-Centric In-Memory Computing for Artificial Intelligence and Neural Network Applications
Sharma, K., Ahir, J., & Singh, L. (2025) · IEEE World Conference on Applied Intelligence and Computing (AIC) · doi:10.1109/aic66080.2025.11212090 · Cited by 1
A Robust 4T1C eDRAM Compute-in-Memory Architecture for Inference Applications
Singh, A. K., Kushwaha, D., & Dasgupta, S. (2025) · IEEE Interregional NEWCAS Conference (NEWCAS) · doi:10.1109/newcas64648.2025.11106976
“Therefore, an efficient processing system is needed to accelerate the DNNs at edge device applications [2].”
Wang, X., Jiao, T.-H., Li, S.-C., Ma, Y., Zhang, Z.-C., Liu, Z., Chen, X., & Si, X. (2025) · Asia and South Pacific Design Automation Conference · doi:10.1145/3658617.3697577
“Currently, a significant amount of research focuses on analog computing-in-memory (ACIM), but this approach is susceptible to PVT variations, leading to precision loss, and demands high-power-consuming peripherals like digital-to-analog converters (DAC) and analog-to-digitalconverters(ADC)[3,4].”
Self-citationAndo, S., Chen, Y.-C., Miyagi, S., Zhang, W., & Yoshioka, K. (2024) · Japanese Journal of Applied Physics · doi:10.35848/1347-4065/ad9611
A 10-MS/s Binary Weight-merged SAR ADC for Real-Time Health-Monitoring System Applications
Chang, Y.-W., Ku, M.-Y., Lee, S.-Y., & Chen, J.-Y. (2024) · Asia Pacific Conference on Circuits and Systems · doi:10.1109/apccas62602.2024.10808612
TimeFloats: Train-in-Memory with Time-Domain Floating-Point Scalar Products
Hashem, M. B., Parpillon, B., Kumar, D., Jayasuriya, D., & Trivedi, A. R. (2024) · International Conference on VLSI Design · doi:10.1109/vlsid64188.2025.00101
Approximate ADCs for In-Memory ComputingPreprint
Ghosh, A., Sadana, H. R., Debnath, M., Maji, P., Negi, S., Gupta, S., Sharad, M., & Roy, K. (2024) · arXiv (Cornell University) · doi:10.48550/arxiv.2408.06390
“Single slope ADC (SS-ADC) [46], as well as Successive Approximation Register ADC (SAR-ADC) [45, 46], have been used for current-mode IMCs.”
MethodA Compact and Low-Power Column Readout Circuit based on Digital Delay Chain
Yang, M., Park, C., & Jung, W. (2024) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas58744.2024.10558326
“Similarly, the ADC faces limitations in terms of power efficiency and required physical area, due to an integrator in single-slope ADCs [4] or a large number of comparators in flash ADCs [5] [6] [7].”
BackgroundComputing-in-memory circuits and cross-layer integrated design and optimization: from SRAM to FeFET
尹, 勋., 岳, 金., 黄, 庆., 李, 超., 蔡, 嘉., 杨, 泽., 卓, 成., & 刘, 明. (2022) · Scientia Sinica Informationis · doi:10.1360/ssi-2021-0420 · Cited by 1
PERCEL: A Rewritable NVM CIM Incorporating a CTT-Based Per-Cell DAC
Chakrabarty, S., Jacob, V., Zeinali, M., Karfakis, G., Qiao, S., Guo, Z., Gupta, P., Iyer, S., & Pamarti, S. (2026) · IEEE Journal on Exploratory Solid-State Computational Devices and Circuits · doi:10.1109/jxcdc.2026.3680497
“Multilevel activation (‘‘n’’bIN × 1bW) has also been explored [6], [10], [11].”
Wang, B., Zhong, X.-X., & Yang, J. (2025) · IEEE Access · doi:10.1109/access.2025.3574524
“3, existing CIM works typically employ a local bit-wise MAC (LBW-MAC) method [1], [2], [3], [4], [5], [7], [10], [12], [13].”
Metadata
- Authors
- Su, J.-W., Chou, Y.-C., Liu, R., Liu, T.-W., Lu, P.-J., Wu, P.-C., Chung, Y.-L., Hung, L.-Y., Ren, J.-S., Pan, T., Li, S.-H., Chang, S.-C., Sheu, S.-S., Lo, W.-C., Wu, C.-I., Si, X., Lo, C.-C., Liu, R.-S., Hsieh, C.-C., Tang, K.-T., & Chang, M.-F.
- Affiliations
- National Tsing Hua University (TW)
- Industrial Technology Research Institute (TW)
- ORCID
- Venue
- 2021 IEEE International Solid-State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Published
- 2021-02-13
- Pages
- 250-252
- ISSN
- 0193-6530 (ISSN-L)
- OpenAlex
- W3133754064
- Cited by
- 207
- References
- 0
- Citations by year
- 2026: 21 · 2025: 35 · 2024: 34 · 2023: 54 · 2022: 52 · 2021: 11
- FWCI
- 59.27
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference (publishedVersion)
- Funders
- Nova
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Keywords
- in-memory computing, 6T SRAM, multiply-accumulate operations, energy efficiency, process variation, analog readout
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