An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology
Abstract
Chronic recording of neural signals is indispensable in designing efficient brain-machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode-neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal-oxide-semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 μA, modulating input referred noise from 9.92 μV to 3.9 μV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.
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Another power-scheduling method is to adapt each amplifier channel's current consumption according to the background noise at its respective electrode.
“Therefore, another power-scheduling method is to adapt the current consumption of each amplifier channel according to the background noise present at the respective electrode [17, 122, 141].”
From Implantable neurotechnologies: a review of integrated circuit neural amplifiers (2016) · cites this paper as [17]
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- Authors
- Chaturvedi, V., & Amrutur, B.
- Affiliations
- Indian Institute of Science Bangalore (IN)
- Venue
- IEEE Journal on Emerging and Selected Topics in Circuits and Systems
- Published
- 2011-12
- Volume
- 1
- Issue
- 4
- Pages
- 536-545
- ISSN
- 2156-3357 (ISSN-L)
- 2156-3365
- OpenAlex
- W2163493252
- Cited by
- 60
- References
- 43
- Citations by year
- 2026: 2 · 2025: 3 · 2024: 5 · 2023: 4 · 2022: 6 · 2021: 4 · 2020: 4 · 2019: 4 · 2018: 5 · 2017: 5 · 2016: 3 · 2015: 8 · 2014: 2 · 2013: 4 · 2012: 1
- FWCI
- 1.33
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Journal on Emerging and Selected Topics in Circuits and Systems (publishedVersion)
- NOT FOUND REPOSITORY (Indian Institute of Science Bangalore) (acceptedVersion)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Life Sciences › Neuroscience › Cellular and Molecular Neuroscience › Neuroscience and Neural Engineering
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Keywords
- neural amplifier, input-referred noise, low noise amplifier, neural recording, microelectrode arrays, brain-computer interface, noise efficiency factor, transistor sizing, 130 nm CMOS, area-efficient design
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